IP Library Granted Patent US 12,609,511
Granted Patent B2
US 12,609,511 · App. 17/655,508 · Granted Apr 21, 2026

Semiconductor optical integrated device

Inventors: Koichiro Iwamoto (Tokyo, JP); Shunya Yamauchi (Kanagawa, JP)
Assignee: Lumentum Radiant GmbH
H01S5/227H01S5/04254H01S5/04256
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Quick Facts
Patent No.
US 12,609,511
App. No.
17/655,508
Granted
Apr 21, 2026
Kind
B2
Abstract

A device includes: a mesa stripe structure comprising a semiconductor in a stripe shape extending in a first direction, with first and second portions spaced apart in the first direction, and a third portion between the first and second portions; and an electrode pattern including a first electrode overlapping with the first portion but not overlapping with the second portion, and a second electrode overlapping with the second portion but not overlapping with the first portion. The first and second electrodes are separated. The electrode pattern comprises a metal in a shape of not overlapping with the third portion. The electrode pattern includes an adjacent area not overlapping with the mesa stripe structure. The adjacent area is next to the third portion in a second direction orthogonal to the first direction, and is on a semiconductor layer continuous to the mesa stripe structure.

Claims (42)

1 . A semiconductor optical integrated device comprising:

a mesa stripe structure in a stripe shape extending in a first direction, the mesa stripe structure having a first portion and a second portion spaced apart and arranged in the first direction, the mesa stripe structure having a third portion between the first portion and the second portion, the mesa stripe structure comprising a semiconductor; and

an electrode pattern including a first electrode that overlaps with the first portion but does not overlap with the second portion, the electrode pattern including a second electrode that overlaps with the second portion but does not overlap with the first portion, the first electrode and the second electrode being separated, the electrode pattern comprising a metal in a shape of not overlapping with the third portion,

the electrode pattern including:

a third electrode that is separated from the first electrode and the second electrode,

wherein the third electrode is not electrically connected to the mesa stripe structure, and

wherein the third electrode is configured to relieve unevenness of stress on the mesa stripe structure; and

an adjacent area, that is part of the third electrode, not overlapping with the mesa stripe structure, the adjacent area being next to the third portion in a second direction orthogonal to the first direction, the adjacent area being on a semiconductor layer continuous to the mesa stripe structure.

2 . The semiconductor optical integrated device according to claim 1 , wherein the semiconductor layer is in contact with a side of the mesa stripe structure.

3 . The semiconductor optical integrated device according to claim 1 , wherein the third electrode is a right-side electrode and a left-side electrode sandwiching the mesa stripe structure in the second direction.

4 . The semiconductor optical integrated device according to claim 3 , wherein the right-side electrode and the left-side electrode are equal in planar size.

5 . The semiconductor optical integrated device according to claim 1 , wherein the third electrode is next, in the second direction, to at least part of the first electrode and at least part of the second electrode.

6 . The semiconductor optical integrated device according to claim 5 , wherein the third electrode is next, in the second direction, to the entire first electrode and the entire second electrode.

7 . The semiconductor optical integrated device according to claim 1 , wherein the adjacent area is a pair of adjacent areas sandwiching the mesa stripe structure.

8 . The semiconductor optical integrated device according to claim 1 , wherein the separation of the first electrode and the second electrode is based on being configured to be electrically insulated from each other.

9 . The semiconductor optical integrated device according to claim 1 , wherein the third electrode is separated from the first electrode and the second electrode based on the third electrode being configured to be electrically insulated from the first electrode and the second electrode.

10 . The semiconductor optical integrated device according to claim 1 , wherein the adjacent area is configured to sandwich the mesa stripe structure.

11 . The semiconductor optical integrated device according to claim 1 , wherein the adjacent area is configured to sandwich the mesa stripe structure below the electrode pattern.

12 . A device comprising:

a mesa stripe structure in a stripe shape extending in a first direction, the mesa stripe structure having a first portion and a second portion spaced apart and arranged in the first direction, the mesa stripe structure having a third portion between the first portion and the second portion, the mesa stripe structure comprising a semiconductor; and

an electrode pattern including a first electrode that overlaps with the first portion but does not overlap with the second portion, the electrode pattern including a second electrode that overlaps with the second portion but does not overlap with the first portion, the first electrode and the second electrode being separated, the electrode pattern comprising a metal in a shape of not overlapping with the third portion,

the electrode pattern including:

a third electrode that is separated from the first electrode and the second electrode,

wherein the third electrode is not electrically connected to the mesa stripe structure, and

wherein the third electrode is configured to relieve unevenness of stress on the mesa stripe structure; and

an adjacent area, that is part of the third electrode, not overlapping with the mesa stripe structure, the adjacent area being next to the third portion in a second direction orthogonal to the first direction, the adjacent area being on a semiconductor layer continuous to the mesa stripe structure.

13 . The device of claim 12 , wherein the third electrode is a right-side electrode and a left-side electrode sandwiching the mesa stripe structure in the second direction.

14 . The device of claim 13 , wherein the right-side electrode and the left-side electrode are equal in planar size.

15 . The device of claim 12 , wherein the adjacent area is configured to sandwich the mesa stripe structure.

16 . A method, comprising:

operating an optical integrated device, wherein the optical integrated device comprises:

a mesa stripe structure in a stripe shape extending in a first direction, the mesa stripe structure having a first portion and a second portion spaced apart and arranged in the first direction, the mesa stripe structure having a third portion between the first portion and the second portion, the mesa stripe structure comprising a semiconductor; and

an electrode pattern including a first electrode that overlaps with the first portion but does not overlap with the second portion, the electrode pattern including a second electrode that overlaps with the second portion but does not overlap with the first portion, the first electrode and the second electrode being separated, the electrode pattern comprising a metal in a shape of not overlapping with the third portion,

the electrode pattern including:

a third electrode that is separated from the first electrode and the second electrode,

 wherein the third electrode is not electrically connected to the mesa stripe structure, and

 wherein the third electrode is configured to relieve unevenness of stress on the mesa stripe structure; and

an adjacent area, that is part of the third electrode, not overlapping with the mesa stripe structure, the adjacent area being next to the third portion in a second direction orthogonal to the first direction, the adjacent area being on a semiconductor layer continuous to the mesa stripe structure.

17 . The method of claim 16 , wherein the third electrode is a right-side electrode and a left-side electrode sandwiching the mesa stripe structure in the second direction.

18 . The method of claim 17 , wherein the right-side electrode and the left-side electrode are equal in planar size.

19 . The method of claim 16 , wherein the adjacent area is configured to sandwich the mesa stripe structure.

20 . The method of claim 16 , wherein the separation of the first electrode and the second electrode is based on being configured to be electrically insulated from each other.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: LUMENTUM JAPAN, INC.
To: LUMENTUMRADIANT GMBH
Reel/Frame 073971/0379 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2022
From: IWAMOTO, KOICHIRO; YAMAUCHI, SHUNYA
To: LUMENTUM JAPAN, INC.
Reel/Frame 059313/0701 →