Device with multi-channel bonding

1. A system comprising:

a primary integrated circuit comprising:

a first primary communication interface configured to receive a first subset of data packets over a first set of channels where each packet of the data packets is associated with a respective sequence number, and each packet of the first subset of the data packets is associated with a first set of sequence numbers;

a second primary communication interface configured to receive a second set of sequence numbers; and

a third primary communication interface configured to cause the first subset of the data packets to be stored in a buffer; and

a secondary integrated circuit comprising:

a first secondary communication interface configured to receive a second subset of the data packets over a second set of channels where each packet of the second subset of the data packets is associated with the second set of sequence numbers;

a second secondary communication interface configured to transmit the second set of sequence numbers to the primary integrated circuit via the second primary communication interface; and

a third secondary communication interface configured to cause the second subset of the data packets to be stored in the buffer,

wherein the third primary communication interface is configured to cause the buffer to be released based on the respective sequence number of each packet, the buffer being associated with the first subset of the data packets and the second subset of the data packets.

2. The system of claim 1 , further comprising a data source communicatively coupled to the primary integrated circuit via the first primary communication interface and to the secondary integrated circuit via the first secondary communication interface.

3. The system of claim 2 , wherein the data source is a cable modem termination system.

4. The system of claim 2 , wherein the respective sequence number associated with each packet of the data packets includes a sequential order assigned by the data source.

5. The system of claim 4 , wherein the primary integrated circuit is configured to cause the buffer to be released based on the sequential order.

6. The system of claim 1 , wherein the first set of sequence numbers are sequentially ordered, and the second set of sequence numbers are sequentially ordered.

7. The system of claim 6 , wherein at least one sequence number from the second set of sequence numbers comes before at least one sequence number from the first set of sequence numbers.

8. The system of claim 1 , further comprising a network processing device communicatively coupled to the primary integrated circuit via the third primary communication interface and to the secondary integrated circuit via the third secondary communication interface, wherein in response to the primary integrated circuit causing the buffer to release a first data packet, the network processing device receives the first data packet.

9. The system of claim 8 , further comprising a memory communicatively coupled to the network processing device and configured to receive the first subset of the data packets from the primary integrated circuit and the second subset of the data packets from the secondary integrated circuit.

10. The system of claim 8 , further comprising a communication device communicatively coupled to the network processing device and configured to transmit the first data packet in response to receiving the first data packet from the network processing device.

11. The system of claim 10 , the primary integrated circuit, the secondary integrated circuit, and the network processing device are disposed in a first device and the communication device is disposed in a second device.

12. The system of claim 1 , wherein the first set of channels comprises one or more first upstream channels and one or more first downstream channels, and the second set of channels comprises one or more second upstream channels and one or more second downstream channels.

13. The system of claim 12 , wherein the first subset of data packets are transmitted over the first downstream channels and the second subset of data packets are transmitted over the second downstream channels.

14. The system of claim 1 , further comprising a tertiary integrated circuit comprising:

a first tertiary communication interface configured to receive a third subset of the data packets over a third set of channels where each packet of the data packets is associated with a third set of sequence numbers;

a second tertiary communication interface configured to transmit the third set of sequence numbers to the primary integrated circuit via the second primary communication interface; and

a third tertiary communication interface configured to transmit the third subset of the data packets.