Queue circuit for controlling access to a memory circuit
A queue circuit that manages access to a memory circuit in a computer system includes multiple sets of entries for storing access requests. The entries in one set of entries are assigned to corresponding sources that generate access requests to the memory circuit. The entries in the other set of entries are floating entries that can be used to store requests from any of the sources. Upon receiving a request from a particular source, the queue circuit checks the entry assigned to the particular source and, if the entry is unoccupied, the queue circuit stores the request in the entry. If, however, the entry assigned to the particular source is occupied, the queue circuit stores the request in one of the floating entries.
1. An apparatus, comprising:
a plurality of sources, including at least one processor core, configured to generate a plurality of requests to access a memory circuit; and
a queue circuit including a first plurality of entries and a second plurality of entries, wherein each entry of the first plurality of entries is assigned to a particular source from the plurality of sources based on which source is used to generate a given request from the plurality of requests, such that each entry of the first plurality of entries is dedicated to at least one source from the plurality of sources, wherein the queue circuit is configured to:
store the given request of the plurality of requests in a particular entry of the second plurality of entries in a storage circuit in response to a determination that an assigned entry of the first plurality of entries assigned to the particular source of the plurality of sources that generated the given request is occupied, wherein the queue circuit is configured to store the given request in a particular entry of a plurality of floating entries, wherein the plurality of floating entries is configured to be dynamically distributed to different sources to accommodate periods where a number of access requests is greater than a typical number of access requests; and
send a previously stored request to the memory circuit.
2. The apparatus of claim 1 , wherein the queue circuit is further configured to store a different request of the plurality of requests in a different entry of the first plurality of entries assigned to a different source of the plurality of sources that generated the different request, in response to a determination that the different entry is unoccupied.
3. The apparatus of claim 1 , wherein the queue circuit is further configured to send a stall signal to a different source of the plurality of sources in response to a determination that a different entry of the first plurality of entries assigned to the different source is occupied, and an unoccupied entry of the second plurality of entries is not available.
4. The apparatus of claim 1 , wherein to send the previously stored request to the memory circuit, the queue circuit is further configured to deallocate a corresponding entry in the first plurality of entries or the second plurality of entries where the previously stored request was located.
5. The apparatus of claim 1 , wherein the memory circuit includes a cache memory circuit that includes multiple banks.
6. The apparatus of claim 1 , wherein the plurality of sources includes a plurality of processor circuits configured to generate corresponding ones of the plurality of requests.
7. A method, comprising:
receiving, from a plurality of sources that includes at least one processor circuit, a plurality of requests to access a memory circuit;
tracking respective status of a first plurality of entries in a storage circuit, wherein each entry of the first plurality of entries is assigned to a particular source from the plurality of sources based on which source is used to generate a given request from the plurality of requests, such that each entry of the first plurality of entries is dedicated to at least one source from the plurality of sources;
storing the given request of the plurality of requests in a particular entry of a second plurality of entries in the storage circuit in response to determining that an assigned entry of the first plurality of entries assigned to the particular source of the plurality of sources that generated the given request is occupied, wherein the queue circuit is configured to store the given request in a particular entry of a plurality of floating entries, wherein the plurality of floating entries is configured to be dynamically distributed to different sources to accommodate periods where a number of access requests is greater than a typical number of access requests; and
sending a previously stored request to the memory circuit.
8. The method of claim 7 , further comprising storing a different request of the plurality of requests in a different entry of the first plurality of entries assigned to a different source of the plurality of sources that generated the different request in response to determining that the different entry is unoccupied.
9. The method of claim 7 , further comprising sending a stall signal to a different source of the plurality of sources in response to determining that a different entry of the first plurality of entries assigned to the different source is occupied and an unoccupied entry of the second plurality of entries is not available.
10. The method of claim 7 , wherein sending the previously stored request to the memory circuit includes deallocating a corresponding entry in the first plurality of entries or the second plurality of entries where the previously stored request was located.
11. The method of claim 7 , wherein the memory circuit includes a cache memory circuit that includes multiple banks.
12. The method of claim 7 , further comprising, generating the plurality of requests by a corresponding plurality of processor circuits.
13. The method of claim 7 , further comprising, generating the plurality of requests by the at least one processor circuit executing a corresponding a plurality of threads.
14. An apparatus, comprising:
a plurality of bank circuits including respective pipeline circuits; and
a control circuit configured to:
receive, from a plurality of sources that includes at least one processor circuit, a plurality of access requests; and
route a given request of the plurality of requests to a particular bank circuit of the plurality of bank circuits, wherein the particular bank circuit includes a storage circuit and a pipeline circuit that includes a queue circuit including a first plurality of entries and a second plurality of entries configured to store the given request in a particular entry of a plurality of floating entries, in response to a determination that an assigned entry of a plurality of assigned entries assigned to a particular source of the plurality of sources that generated the given request is occupied, wherein the plurality of floating entries are dynamically distributed to different sources to accommodate periods where a number of access requests is greater than a typical number of access requests, wherein each entry of the first plurality of entries is assigned to a particular source from the plurality of sources based on which source is used to generate the given request from the plurality of requests, such that each entry of the first plurality of entries is dedicated to at least one source from the plurality of sources.
15. The apparatus of claim 14 , wherein the control circuit is further configured to route a different request of the plurality of requests to the particular bank circuit, and wherein the queue circuit is further configured to store the different request of the plurality of requests in a different entry of the plurality of assigned entries assigned to a different source of the plurality of sources that generated the different request in response to a determination that the different entry is unoccupied.
16. The apparatus of claim 14 , wherein the queue circuit is further configured to send a stall signal to a different source of the plurality of sources in response to a determination that a different entry of the plurality of assigned entries assigned to the different source is occupied and an unoccupied entry of plurality of the floating entries is not available.
17. The apparatus of claim 14 , wherein the queue circuit is further configured to send a particular request previously stored in an occupied entry in either the plurality of assigned entries or the plurality of floating entries to the storage circuit.
18. The apparatus of claim 17 , wherein the queue circuit is further configured to deallocate the occupied entry in response to sending the particular request to the storage circuit.
19. The apparatus of claim 14 , wherein the plurality of sources includes a plurality of processor circuits configured to generate the plurality of requests.
20. The apparatus of claim 14 , wherein the at least one processor circuit is configured to execute a plurality of threads to generate the plurality of requests.