Technique for Overriding Memory Attributes

1 . An apparatus, comprising:

a plurality of memory access control registers that are programmable with respective address ranges within an address space; and

a memory access circuit configured to:

generate a command for performing a memory access, the command specifying an address corresponding to a location in a memory circuit; and

in response to the address being located within an address range of a particular one of the plurality of memory access control registers, perform the command using override memory parameters that have been programmed into the particular memory access control register instead of a default set of attributes for the address space, wherein at least one value of the override memory parameters that have been programmed into the particular memory access control register is appended to the command.

2 . The apparatus of claim 1 , wherein the memory access circuit is further configured to:

generate a different command for performing a different memory access, the command specifying a different address that is located within the address range of the particular memory access control register; and

in response to the different address being located within an address range of a different one of the plurality of memory access control registers, perform the command using override memory parameters that have been programmed into the different memory access control register instead of the override memory parameters of the particular memory access control register, wherein the different memory access control register has a higher priority than the particular memory access control register.

3 . The apparatus of claim 1 , wherein each of the plurality of memory access control registers is assigned a respective priority, and wherein the memory access circuit is further configured to use the override memory parameters from the particular memory access control register in response to a determination that the particular memory access control register has a higher priority than other memory access control registers that have corresponding address ranges.

4 . The apparatus of claim 1 , wherein the memory access circuit includes:

an instruction fetch circuit configured to use the plurality of programmable memory access control registers for memory access commands; and

a load-store circuit configured to use a different plurality of programmable memory access control registers for memory access commands.

5 . The apparatus of claim 1 , wherein the memory access circuit includes:

an instruction fetch circuit configured to use a first set of comparators to compare addresses of memory access commands from the instruction fetch circuit to the plurality of programmable memory access control registers; and

a load-store circuit configured to use a second set of comparators to compare addresses of memory access commands from the load-store circuit to the plurality of programmable memory access control registers.

6 . The apparatus of claim 1 , wherein ones of the plurality of memory access control registers include an address mask field, and wherein a value of the address mask field determines a start address and a size of a respective address range for a given memory access control register.

7 . The apparatus of claim 1 , wherein to perform the command using the override memory parameters, the memory access circuit is configured to append at least one override memory parameter from the particular memory access control register to the command.

8 . A method, comprising:

initializing, by a processor, at least one of a plurality of programmable memory access control registers with respective address values, the respective address values indicating a corresponding address range within an address space;

creating, by a memory access circuit in the processor, a command for performing a memory access, the command specifying an address corresponding to a location in a memory circuit; and

in response to determining that the address is located within an address range of a particular one of the plurality of memory access control registers, performing, by the memory access circuit, the command using override memory parameters that have been programmed into the particular memory access control register instead of a default set of attributes for the address space, wherein at least one value of the override memory parameters that have been programmed into the particular memory access control register is appended to the command.

9 . The method of claim 8 , wherein ones of the plurality of memory access control registers have respective priority levels based on respective locations of the plurality of memory access control registers within a register block.

10 . The method of claim 9 , wherein determining that the address is located within the address range of the particular one of the plurality of memory access control registers includes:

comparing a portion of the specified address to a respective address value included in a different one of the plurality of memory access control registers, the different memory access control register having a higher priority than the particular memory access control register; and

in response to determining that the portion of the specified address does not correspond to the different memory access control register, comparing the portion of the specified address to the respective address value of the particular memory access control register.

11 . The method of claim 8 , wherein the default set of attributes for the address space includes:

an indication of whether information in a given address is cacheable; and

an indication of whether information in a given address has side-effects when accessed.

12 . The method of claim 8 , further comprising:

mapping the specified address of the command from a virtual address to a physical address; and

comparing the physical address to the address range of the particular memory access control register.

13 . The method of claim 8 , wherein the respective address values indicate both a starting address and a size of the corresponding address range.

14 . A system, comprising:

a memory interface circuit configured to access one or more memory circuits based on a system memory map using a default set of attributes for an address space associated with the system memory map; and

a plurality of processor cores, wherein ones of the processor cores include a respective set of memory access control registers including a programmable address field indicative of an address range in the system memory map, and an attribute override field; and

wherein a particular processor core of the plurality of processor cores is configured to:

generate a command for performing a memory access, the command specifying a target address corresponding to a location in the system memory map;

compare the target address to an address range indicated by one or more of the respective sets of memory access control registers; and

in response to a determination that the target address is located within a particular address range of a particular one of the one or more memory access control registers, send the command to the memory interface circuit using the respective attribute override field of the particular memory access control register wherein at least one value of the override memory parameters that have been programmed into the particular memory access control register is appended to the command.

15 . The system of claim 14 , wherein one of the processor cores include a respective local memory space, including one or more registers;

wherein a local memory space for the particular processor core is not accessible by other ones of the plurality of processor cores; and

wherein the particular processor core is further configured to use a default set of attributes for the local memory space.

16 . The system of claim 15 , wherein the particular processor core is further configured to store a particular value to at least one of the respective set of memory access control registers; and

wherein the particular value determines one or more attribute override values for at least a portion of the local memory space.

17 . The system of claim 14 , wherein a different processor core of the plurality of processor cores is configured to:

receive a different command for performing a memory access, the command specifying the target address;

compare the target address to an address range indicated by one or more respective memory access control registers of the different processor cores; and

in response to a determination that the target address is located within a particular address range of a different one of the one or more memory access control registers of the different processor core, send the command to the memory interface circuit using the respective attribute override field of the different memory access control register, wherein the attribute override field of the different memory access control register has a different value than the attribute override field of the particular memory access control register.

18 . The system of claim 14 , further including a set of global memory access control registers accessible to the plurality of processor cores.

19 . The system of claim 18 , wherein the particular processor core is further configured to:

compare the target address to an address range indicated by one or more of the global memory access control registers;

in response to a determination that the target address is located within a given address range of a given one of the global memory access control registers, determine a priority between the given global memory access control register and the particular memory access control register; and

send the command to the memory interface circuit using the respective attribute override field of the particular memory access control register in response to a determination that the particular memory access control register has a higher priority than the given global memory access control register.

20 . The system of claim 19 , wherein the address range of the particular memory access control register is smaller than the address range of the given global memory access control register.