Barrier-free approach for forming contact plugs
A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer.
1. An integrated circuit structure comprising:
a dielectric layer;
a metal ring contacting sidewalls of the dielectric layer;
a metal region encircled by the metal ring; and
a silicon-and-nitrogen rich layer between the metal ring and the metal region, wherein a silicon atomic percentage in the silicon-and-nitrogen rich layer is higher than silicon atomic percentages in both of the metal ring and the metal region, and a first nitrogen atomic percentage in the silicon-and-nitrogen rich layer is higher than second nitrogen atomic percentages in the metal ring and the metal region.
2. The integrated circuit structure of claim 1 further comprising:
a semiconductor region underlying the dielectric layer; and
a metal silicide region on top of the semiconductor region, wherein the metal silicide region is overlapped by the metal region, and wherein the silicon-and-nitrogen rich layer further extends into a region between the metal silicide region and the metal region.
3. The integrated circuit structure of claim 1 , wherein the metal ring and the metal region comprise different metals.
4. The integrated circuit structure of claim 3 , wherein the metal ring comprises titanium, and the metal region comprises cobalt.
5. The integrated circuit structure of claim 1 , wherein the dielectric layer comprises a silicon-base dielectric material.
6. The integrated circuit structure of claim 1 further comprising:
an inter-layer dielectric over the dielectric layer;
a metal contact plug in the inter-layer dielectric, wherein the metal contact plug is over and contacting the metal region; and
a nitrogen-rich layer between the inter-layer dielectric and the metal contact plug, wherein a third nitrogen atomic percentage in the nitrogen-rich layer is higher than a fourth nitrogen atomic percentage in the metal contact plug.
7. The integrated circuit structure of claim 6 , wherein the metal contact plug and the metal region are free from nitrogen-rich layers in between.
8. The integrated circuit structure of claim 1 , wherein the silicon-and-nitrogen rich layer forms Si—N-metal bonds with the metal region.
9. The integrated circuit structure of claim 1 , wherein the metal region is a barrier-less metal region formed of a homogeneous material.
10. The integrated circuit structure of claim 9 , wherein the homogeneous material comprises cobalt.
11. An integrated circuit structure comprising:
a semiconductor region;
a gate stack on the semiconductor region;
a source/drain region on a side of the gate stack;
a source/drain silicide region over and contacting the source/drain region;
a silicon nitride layer comprising a first portion over and contacting the source/drain silicide region; and
a contact plug over and contacting the silicon nitride layer.
12. The integrated circuit structure of claim 11 , wherein the silicon nitride layer further comprises a second portion encircling the contact plug.
13. The integrated circuit structure of claim 12 further comprising:
a metal layer encircling the contact plug; and
an inter-layer dielectric encircling the metal layer, wherein the second portion of the silicon nitride layer is between the metal layer and the contact plug.
14. The integrated circuit structure of claim 11 , wherein the silicon nitride layer is bonded with a metal in the contact plug to form Si—N-metal bonds.
15. The integrated circuit structure of claim 11 , wherein the contact plug is barrier-less.
16. An integrated circuit structure comprising:
a conductive layer;
a plurality of dielectric layers over and contacting the conductive layer;
a silicon nitride layer comprising:
a sidewall portion contacting sidewalls of the plurality of dielectric layers; and
a bottom portion overlapping and contacting the conductive layer; and
a metallic region encircled by the silicon nitride layer, wherein the metallic region is formed of a homogeneous material, and wherein the metallic region is separated from the conductive layer by the bottom portion of the silicon nitride layer.
17. The integrated circuit structure of claim 16 , wherein the silicon nitride layer is a mono-layer.
18. The integrated circuit structure of claim 16 , wherein the bottom portion of the silicon nitride layer comprises a top surface contacting a bottom surface of the metallic region.
19. The integrated circuit structure of claim 16 , wherein the conductive layer comprises a metal silicide.
20. The integrated circuit structure of claim 19 further comprises a source/drain region underlying the metal silicide.