IP Library Granted Patent US 11,856,364
Granted Patent B2
US 11,856,364 · App. 17/665,041 · Granted Dec 26, 2023

Microphone array system with sound wire interface and electronic device

Inventor: Jinghua Ye (Shanghai, CN)
Assignee: ZILLTEK TECHNOLOGY CORP.
H04R1/406H04R3/005G10L2021/02166H04R2201/401
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Quick Facts
Patent No.
US 11,856,364
App. No.
17/665,041
Granted
Dec 26, 2023
Kind
B2
Abstract

A microphone array system, comprises N microphones, including a first microphone . . . a Nth microphone, wherein N is a natural number greater than 2. Each of the N microphones is provided with: an acoustic transducer for picking up a sound signal and converting the sound signal into an electric signal; a voice activation detector, connected to a corresponding acoustic transducer, and configured to perform a voice activation detection on the electric signal and form an activation signal; a buffer memory, connected to the acoustic transducer, and configured to store a 1/N electric signal of a predetermined segment; a sound wire interface, connected to a corresponding acoustic transducer, the buffer memory, and the voice activation detector, wherein the sound wire interface is connected to an external master chip via a sound wire bus for outputting the activation signal to the external master chip.

Claims (13)

1. A microphone array system with a sound wire interface, comprising N microphones, wherein N is a natural number greater than 2, each of the N microphones is provided with:

an acoustic transducer for picking up a sound signal and converting the sound signal into an electric signal;

a voice activation detector, connected to a corresponding acoustic transducer, and configured to perform a voice activation detection on the electric signal and form an activation signal;

a buffer memory, connected to the acoustic transducer, and configured to store a 1/N predetermined segment of the electric signal;

a sound wire interface, connected to the corresponding acoustic transducer, the buffer memory, and the voice activation detector, wherein the sound wire interface is connected to an external master chip via a sound wire bus for outputting the activation signal to the external master chip.

2. The microphone array system with the sound wire interface of claim 1 , wherein the buffer memory of the first microphone is recorded as a first buffer memory, the first buffer memory stores a first 1//N electric signal of a predetermined segment, the buffer memory of the Nth microphone is recorded as a Nth buffer memory, the Nth buffer memory stores a Nth 1//N electric signal of a predetermined segment.

3. The microphone array system with the sound wire interface of claim 1 , wherein the activation signals output from the voice activation detectors of the N microphones are output via corresponding sound wire interfaces.

4. The microphone array system with the sound wire interface of claim 1 , wherein the external master chip reads the electric signal of the predetermined segment stored in the buffer memory of each of the N microphones in sequence, and performs a voice recognition on the electric signal of the predetermined segment.

5. The microphone array system with the sound wire interface of claim 4 , wherein an end of the electric signal of the predetermined segment stored in the buffer memory is provided with an end flag bit, upon reading the end flag bit of the buffer memory of each of the N microphones, the external master chip reads the electric signal of the predetermined segment stored in the buffer memory of the subsequent microphone.

6. A control method of the microphone array system with the sound wire interface of claim 1 , wherein after receiving the activation signal, the external master chip generates a system wake-up signal, the buffer memory of the microphone concurrently stores the 1/N electric signal of the predetermined segment, collected by the acoustic transducer, in parallel.

7. An electronic device comprising the microphone array system with the sound wire interface of claim 1 and the external master chip.

8. The electronic device of claim 7 , wherein the external master chip reads the electric signal of the predetermined segment stored in the buffer memory of each of the N microphones in sequence, and performs a voice recognition on the electric signal of the predetermined segment.

9. The electronic device of claim 8 , wherein upon reading the end flag bit of the buffer memory of each of the N microphones, the external master chip reads the electric signal of the predetermined segment stored in the buffer memory of the subsequent microphone.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2022
From: YE, JINGHUA
To: ZILLTEK TECHNOLOGY (SHANGHAI) CORP.; ZILLTEK TECHNOLOGY CORP.
Reel/Frame 058895/0466 →
Priority Claims (1)
CN 202110888185.4 · Aug 3, 2021 · national
Continuity (1)
Related Publication 20230043176A1 · Feb 9, 2023