PIN determination for single-conductor interface
Circuits and methods for determining the characteristics of swappable pins in a peripheral in a 1-Wire or similar single-conductor system, thereby allowing each one of two pins to be either an I/O pin (connected to an I/O line) or a CAP pin (connected to a storage capacitor). Embodiments preform the following functions: detecting the initial phase of device startup; determining which of pins A and B is coupled to an I/O line (and thus is the I/O pin), and which is coupled to the storage capacitor (and thus is the CAP pin); and generating a flag signal indicating that determination to other circuitry within the peripheral. Detection of pin characteristics is determined at device startup by latching the fastest rising signal on pins A and B, flagging that signal line as being the I/O line, and preventing further changes to the latch output until the next startup cycle.
1. A circuit for determining the characteristics of respective signals on a first pin and a second pin of a peripheral configured to be coupled to a single-conductor communications bus, the circuit including a latch having first and second inputs respectively coupled to the first and the second pins, wherein the latch is configured to determine which signal on the first and the second pins rises fastest during a startup period and output a first selected logic state indicating that the first pin is coupled to an input/output signal line and the second pin is coupled to a storage capacitor, or a second selected logic state indicating that the first pin is coupled to the storage capacitor and the second pin is coupled to the input/output signal line.
2. The invention of claim 1 , wherein the latch is an active-LOW set-reset latch.
3. The invention of claim 1 , further including a circuit coupled to an internal voltage supply output and configured to generate a power good indication when a voltage on the internal voltage supply output rises above a selected threshold.
4. The invention of claim 3 , wherein the power good indication is coupled to the first and second inputs of the latch so as to prevent alteration of the output states of the latch.
5. The invention of claim 1 , further including a circuit coupled between the latch and the first and second pins, and configured to provide a voltage to the latch that is the greater of a first voltage applied to the first pin and a second voltage applied to the second pin.
6. The invention of claim 1 , further including a first electrostatic discharge circuit coupled to the first pin, and a second electrostatic discharge circuit coupled to the second pin.
7. A circuit for determining the characteristics of respective signals on a first pin and a second pin of a peripheral configured to be coupled to a single-conductor communications bus, the circuit including:
(a) a first switch having a control input and having a conduction channel coupled between the first pin and an internal voltage supply output;
(b) a second switch having a control input and having a conduction channel coupled between the second pin and the internal voltage supply output; and
(c) a latch having first and second inputs respectively coupled to the first and the second pins;
wherein the latch is configured to determine which signal on the first and the second pins rises fastest during a startup period and output a first selected logic state indicating that the first pin is coupled to an input/output signal line and the second pin is coupled to a storage capacitor, or a second selected logic state indicating that the first pin is coupled to the storage capacitor and the second pin is coupled to the input/output signal line; and
wherein the first and second selected logic state outputs of the latch are coupled to respective ones of the control inputs of the first and second switches.
8. The invention of claim 7 , wherein the first and second switches are PFETs.
9. The invention of claim 7 , wherein the latch is an active-LOW set-reset latch.
10. The invention of claim 7 , further including a voltage level translator coupled between the latch and the first and second switches and configured to translate voltages output by the latch to voltage levels compatible with voltages on the internal voltage supply output.
11. The invention of claim 7 , further including a circuit coupled to the internal voltage supply output and configured to generate a power good indication when a voltage on the internal voltage supply output rises above a selected threshold.
12. The invention of claim 11 , wherein the power good indication is coupled to the first and second inputs of the latch so as to prevent alteration of the output states of the latch.
13. The invention of claim 7 , further including a circuit coupled between the latch and the first and second pins, and configured to provide a voltage to the latch that is the greater of a first voltage applied to the first pin and a second voltage applied to the second pin.
14. The invention of claim 7 , further including a first electrostatic discharge circuit coupled to the first pin, and a second electrostatic discharge circuit coupled to the second pin.
15. A circuit for determining the characteristics of respective signals on a first pin and a second pin of a peripheral configured to be coupled to a single-conductor communications bus, the circuit including:
(a) a supply switch circuit including:
(1) a first switch having a control input and having a conduction channel coupled between the first pin and an internal voltage supply output; and
(2) a second switch having a control input and having a conduction channel coupled between the second pin and the internal voltage supply output; and
(b) a latch including:
(1) a first input coupled to the first pin;
(2) a second input coupled to the second pin;
(3) a first output coupled to the control input of the first switch and configured to be in a first logic state if a signal on the first input rises faster than a signal on the second input during a startup period, and configured to be in a second logic state if the signal on the second input rises faster than the signal on the first input during the startup period; and
(4) a second output coupled to the control input of the second switch and configured to be in the first logic state if the signal on the second input rises faster than the signal on the first input during the startup period, and configured to be in the second logic state if a signal on the first input rises faster than a signal on the second input during the startup period;
wherein the first logic state of the first output of the latch indicates that the first pin is coupled to an input/output signal line and the second pin is coupled to a storage capacitor, and wherein the second logic state of the first output of the latch indicates that the first pin is coupled to the storage capacitor and the second pin is coupled to the input/output signal line.
16. The invention of claim 15 , wherein the first and second switches are PFETs.
17. The invention of claim 15 , wherein the latch is an active-LOW set-reset latch.
18. The invention of claim 15 , further including a voltage level translator coupled between the latch and the first and second switches and configured to translate voltages output by the latch to voltage levels compatible with voltages on the internal voltage supply output.
19. The invention of claim 15 , further including a circuit coupled to the internal voltage supply output and configured to generate a power good indication when a voltage on the internal voltage supply output rises above a selected threshold.
20. The invention of claim 19 , wherein the power good indication is coupled to the first and second inputs of the latch so as to prevent alteration of the output states of the latch.
21. The invention of claim 15 , further including a circuit coupled between the latch and the first and second pins, and configured to provide a voltage to the latch that is the greater of a first voltage applied to the first pin and a second voltage applied to the second pin.
22. The invention of claim 15 , further including a first electrostatic discharge circuit coupled to the first pin, and a second electrostatic discharge circuit coupled to the second pin.