METHODS AND SYSTEMS FOR FABRICATION OF VERTICAL FIN-BASED JFETS
A vertical FET device includes a semiconductor structure comprising a semiconductor substrate, a first semiconductor layer coupled to the semiconductor substrate, and a second semiconductor layer coupled to the first semiconductor layer. The vertical FET device also includes a plurality of fins. Adjacent fins of the plurality of fins are separated by a trench extending into the second semiconductor layer and each of the plurality of fins includes a channel region disposed in the second semiconductor layer. The vertical FET also includes a gate region extending into a sidewall portion of the channel region of each of the plurality of fins, a source metal structure coupled to the second semiconductor layer, a gate metal structure coupled to the gate region, and a drain contact coupled to the semiconductor substrate.
1 . A vertical FET device comprising:
a semiconductor structure comprising a semiconductor substrate, a first semiconductor layer coupled to the semiconductor substrate, and a second semiconductor layer coupled to the first semiconductor layer;
a plurality of fins, wherein adjacent fins of the plurality of fins are separated by a trench extending into the second semiconductor layer and wherein each of the plurality of fins includes a channel region disposed in the second semiconductor layer;
a gate region extending into a sidewall portion of the channel region of each of the plurality of fins;
a source metal structure coupled to the second semiconductor layer;
a gate metal structure coupled to the gate region; and
a drain contact coupled to the semiconductor substrate.
2 . The vertical FET device of claim 1 further comprising a drift region disposed in the first semiconductor layer.
3 . The vertical FET device of claim 1 wherein the gate region extends along a horizontal surface of the first semiconductor layer.
4 . The vertical FET device of claim 1 wherein the gate region extends along vertical surfaces of the plurality of fins.
5 . The vertical FET device of claim 1 wherein sidewalls of the plurality of fins include an undiffused section.
6 . The vertical FET device of claim 1 wherein the gate region comprises a p-GaN gate layer.
7 . The vertical FET device of claim 1 wherein a dopant concentration between the gate region and the first semiconductor layer is 1-3×10 19 atoms/cm 3 .
8 . The vertical FET device of claim 1 wherein the gate region comprises a junction depth between 25 and 50 nm.
9 . A method for manufacturing a vertical FET device, the method comprising:
providing a semiconductor substrate;
epitaxially growing a first semiconductor layer coupled to the semiconductor substrate;
epitaxially growing a second semiconductor layer coupled to the first semiconductor layer;
forming a patterned hard mask coupled to the second semiconductor layer;
etching the second semiconductor layer and a portion of the first semiconductor layer to form a plurality of fins;
applying a diffusion dopant layer;
applying a sacrificial planarization layer on the diffusion dopant layer;
selectively etching the sacrificial planarization layer to expose the diffusion dopant layer;
removing an exposed portion of the diffusion dopant layer and the sacrificial planarization layer;
performing a thermal treatment to diffuse the diffusion dopant layer into the first semiconductor layer and form a diffused gate layer;
removing the diffusion dopant layer and the patterned hard mask;
forming a source metal structure coupled to a top surface of the second semiconductor layer;
forming a gate metal structure coupled to the diffused gate layer; and
forming a drain contact coupled to a bottom surface of the semiconductor substrate.
10 . The method of claim 9 further comprising forming an edge termination for the diffused gate layer overlaying a top surface of the first semiconductor layer.
11 . The method of claim 9 wherein the diffusion dopant layer comprises a metal layer formed with a p-type dopant.
12 . The method of claim 9 wherein selectively etching the sacrificial planarization layer comprises a reactive-ion etch.
13 . The method of claim 9 wherein a dopant metallurgical concentration between the diffusion dopant layer and the first semiconductor layer is 1-3×10 19 atoms/cm 3 .
14 . The method of claim 9 wherein the diffused gate layer extends along a portion of sidewalls of the second semiconductor layer.
15 . The method of claim 9 wherein the drain contact comprises titanium, aluminum, or a combination thereof.
16 . A method for manufacturing a conformal-gate vertical FET device, the method comprising:
providing a semiconductor structure including a substrate, a first semiconductor layer, and a second semiconductor layer;
forming a plurality of fins having sidewall surfaces in a portion of the first semiconductor layer and the second semiconductor layer, wherein the plurality of fins are separated by trenches;
growing a third semiconductor layer coupled to the sidewall surfaces of the plurality of fins, wherein the third semiconductor layer includes a dopant and comprises a recessed gate region; and
forming a source metal, a gate metal, and a drain contact.
17 . The method of claim 16 further comprising performing a thermal treatment to activate the dopant in the recessed gate region.
18 . The method of claim 16 wherein the third semiconductor layer extends along a portion of the sidewall surfaces of the plurality of fins.
19 . The method of claim 16 further comprising forming an edge termination for the recessed gate region overlaying a top surface of the first semiconductor layer.
20 . The method of claim 16 wherein the third semiconductor layer comprises a conformal layer.