Methods and systems for establishing direct communications between a server computer and a smart network interface controller

1. Apparatus for performing direct memory access (“DMA”) between memory of a host and memory of a smart network interface controller (“SNIC”) connected to a bus of the host, the apparatus comprising:

a host thread running in a processor of the host for fetching data directly from and writing data directly to the memory of the SNIC over the bus using a first memory address of the memory of the SNIC, the host thread being configured to send a DMA command to the SNIC, the DMA command including a command ID that requests resource allocation for a virtual device function stored in a memory of the SNIC; and

a SNIC thread running in a processor of the SNIC for fetching data directly from and writing data directly to the memory of the host over the bus using a second memory address of the memory of the host, the SNIC thread being configured to, upon completing a data transfer operation, write a completion flag to the memory location or status register with the virtual device function, and to interrupt the host processor to signal completion of the operation.

2. The apparatus of claim 1 wherein the host thread running in the processor of the host for writing data directly to the memory of the SNIC comprises:

sends a DMA command to the SNIC thread that identifies a memory location of the memory of the host;

writes data to the memory location; and

writes a doorbell to a doorbell register of the SNIC, the doorbell indicating data has been written to the memory location.

3. The apparatus of claim 1 wherein the SNIC thread running in a processor of the SNIC for fetching data directly from the memory of the host comprises:

receives a doorbell in a doorbell register of the SNIC, the doorbell indicating data has been written to a memory location in the memory of the host;

fetches the data stored in the memory location; and

writes the data to a memory location in the memory of the SNIC.

4. The apparatus of claim 1 wherein the host thread running in the processor of the host for fetching data directly from the memory of the SNIC comprises:

sends a DMA command to the SNIC thread that identifies a memory location of the memory of the host and directs the SNIC thread to write data to the memory location;

polls the memory location to determine whether data has been written to the memory location; and

fetches data from the memory location in response to detecting data stored at the memory location.

5. The apparatus of claim 1 wherein the host thread running in the processor of the host for fetching data directly from the memory of the SNIC comprises:

sends a DMA command to the SNIC thread that identifies a memory location of the memory of the host and directs the SNIC thread to write data to the memory location;

interrupts the processor of the host; and

fetches data from the memory location in response to detecting data stored at the memory location.

6. The apparatus of claim 1 wherein the SNIC thread running in the processor of the SNIC for writing data directly to the memory of the SNIC comprises:

sends a DMA command to the host thread that identifies a memory location of the memory of the host;

receives a doorbell from the host thread in a doorbell register of the SNIC, the doorbell indicating data has been written to a memory location in the memory of the host;

fetches data stored in the memory location in the memory of the host; and

writes the data to a memory location in the memory of the SNIC.

7. The apparatus of claim 1 wherein the host thread running in a processor of the host for writing data directly from the memory of the host comprises:

receives a DMA command from the SNIC thread that identifies a memory location of the memory of the host;

writes data to the memory location in the memory of the host; and

sends a doorbell to a doorbell register of the SNIC, the doorbell indicating data has been written to the memory location.

8. The apparatus of claim 1 wherein the SNIC thread running in the processor of the SNIC for fetching data directly from the memory of the host comprises:

sends a DMA command to the host thread that identifies a memory location of the memory of the host and directs the host thread to write data to the memory location;

polls the memory location to determine whether data has been written to the memory location;

fetches the data from the memory location in response to detecting the data stored at the memory location; and

writes the data to a memory location in the memory of the SNIC.

9. The apparatus of claim 1 wherein the SNIC thread running in the processor of the SNIC for writing data directly from the memory of the host comprises:

sends a DMA command to the host thread that identifies a memory location in the memory of the host; and

writes data direct to the memory location in the memory of the host.

10. The apparatus of claim 1 wherein the host thread running in the processor of the host for fetching data directly from the memory of the SNIC comprises:

interrupts the processor of the host; and

fetches data from the memory location in the memory of the host.

11. The apparatus of claim 1 , wherein the host thread is configured to send a DMA command that identifies a memory location in the SNIC, the DMA command being sent using a memory-mapped I/O (MMIO) region.

12. A method for performing direct memory access (“DMN”) to memory of a host by a smart network interface controller (“SNIC”) connected to a bus of the host, the method comprising:

sending a DMA command from a host thread that runs in a processor of the host to an SNIC thread that runs in a processor of the SNIC, the DMA command identifying a memory location in the memory of the host using a first memory address of the memory of the SNIC;

writing data from the memory of the SNIC into the memory location in the memory of the host by the SNIC thread using a second memory address of the memory of the host;

sending a DMA command to the SNIC, the DMA command including a command ID that requests resource allocation for a virtual device function stored in a memory of the SNIC

fetching the data from the memory location in the memory of the host by the host thread;

writing a completion flag to the memory location or status register with the virtual device function, and;

interrupting the host processor to signal completion of the operation.

13. The method of claim 12 further comprising polling the memory location in the memory of the host by the host thread.

14. The method of claim 12 further comprising interrupting the processor of the host.

15. A method for performing direct memory access (“DMA”) to memory of a host by a smart network interface controller (“SNIC”) connected to a bus of the host, the method comprising:

receiving a DMA command at a host thread that runs in a processor of the host, the DMA command generated by an SNIC thread that runs in a processor of the SNIC and identifies a memory location in the memory of the host, the DMA command including a command ID that requests resource allocation for a virtual device function stored in a memory of the SNIC;

the host thread writing data to the memory location;

the SNIC thread fetching the data from the memory location using a memory address of the memory of the host; and

the SNIC thread writing the data to a memory location in memory of the SNIC;

the SNIC thread, upon completing a data transfer operation, writing a completion flag to the memory location or status register with the virtual device function, and interrupting the host processor to signal completion of the operation.

16. The method of claim 15 further comprising the host thread sending a doorbell to a doorbell register of the SNIC.

17. The method of claim 15 further comprising the SNIC thread polling the memory location in the memory of the host.