Method and apparatus for gather/scatter operations in a vector processor
In one implementation a vector processor gather/scatter apparatus comprises a plurality of vector ports, and a random access memory, where the plurality of vector ports are in communication with the random access memory, and where one or more of the plurality of vector ports uses one or more of an address register and one or more of a stride register in communication with the random access memory to allow the gather/scatter of random access memory contents.
1. A vector processor gather/scatter apparatus comprising:
a plurality of vector ports;
a random access memory;
the plurality of vector ports in communication with the random access memory; and
wherein one or more of the plurality of vector ports uses a respective address registers and a respective stride registers to generate an autoincrementing address for the random access memory; and
wherein when the autoincrementing address equals, or is greater than, a length value in a respective port's length register for the one or more of the plurality of vector ports, then the respective address register is reset to an original value.
2. The vector processor gather/scatter apparatus of claim 1 wherein the plurality of vector ports can support up to two reads and a write per clock cycle for the random access memory while performing a gather and scatter operation.
3. The vector processor gather/scatter apparatus of claim 1 wherein the plurality of vector ports can support sixteen reads and eight writes per clock cycle for the random access memory.
4. The vector processor gather/scatter apparatus of claim 1 wherein the one or more address registers and the one or more stride registers allow a matrix stored in the random access memory to be accessed along a sequence, the sequence consisting of one or more of the following, along a row of the matrix, along a column of the matrix, and along a diagonal of the matrix.