Word line and control gate line tandem decoder for analog neural memory in deep learning artificial neural network
Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.
1. A tandem row decoder for controlling a word line and a control gate line coupled to a row of non-volatile memory cells in an array, comprising:
a word line decoder to drive the word line; and
a control gate decoder to drive the control gate line;
wherein the word line decoder is enabled by an output of the control gate decoder; and
wherein the array is a neural analog memory.
2. A tandem row decoder for controlling a word line and a control gate line coupled to a row of non-volatile memory cells in an array, comprising:
a word line decoder to drive the word line; and
a control gate decoder to drive the control gate line;
wherein the word line decoder is enabled by an output of the control gate decoder; and
wherein the non-volatile memory cells are split-gate memory cells.
3. A tandem row decoder for controlling a word line and a control gate line coupled to a row of non-volatile memory cells in an array, comprising:
a word line decoder to drive the word line; and
a control gate decoder to drive the control gate line;
wherein the control gate decoder is enabled by an output of the word line decoder; and
wherein the array is a neural analog memory.
4. A tandem row decoder for controlling a word line and a control gate line coupled to a row of non-volatile memory cells in an array, comprising:
a word line decoder to drive the word line; and
a control gate decoder to drive the control gate line;
wherein the control gate decoder is enabled by an output of the word line decoder; and
wherein the non-volatile memory cells are split-gate memory cells.