Memory device including ternary memory cell
Provided is a memory device for a logic-in-memory. The memory cell includes: a ternary memory cell for storing ternary data: and a weight cell for controlling a current flowing in an operation line on the basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, wherein the weight cell includes a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line.
1 . A memory cell in a memory device for a logic-in-memory, the memory cell comprising:
a single ternary memory cell configured to store ternary data having a weight value of one of −1, 0 and +1; and
a weight cell configured to control a current flowing in an operation line on a basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line,
wherein the weight cell comprises a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line,
wherein when the ternary memory cell stores the weight value of −1, the weight data of the first node is 0 and the inversed weight data of the second node is 2,
when the ternary memory cell stores the weight value of 0, the weight data of the first node and the inversed weight data of the second node are 1, and
when the ternary memory cell stores the weight value of +1, the weight data of the first node is 2 and the inversed weight data of the second node is 0.
2 . The memory cell of claim 1 , wherein the first transistor is connected to the first node, the second transistor, and a first operation line,
the second transistor is connected to the second node, the first transistor, and a second operation line, and
the third transistor is connected to a third node that is a junction of the first transistor and the second transistor, and to the activation line.
3 . The memory cell of claim 2 , wherein the ternary memory cell is configured to:
receive the weight data via a first bit line;
receive the inversed weight data via a second bit line; and
output the weight data and the inversed weight data as the weight cell on a basis of an input signal via a word line.
4 . The memory cell of claim 2 , wherein the weight cell is configured to:
receive the weight data and the inversed weight data from the ternary memory cell;
receive the activation signal to activate the weight cell via the activation line; and
block at least one of a first current path along the first operation line and the first transistor or a second current path along the second operation line and the second transistor, on a basis of the weight data and the inversed weight data.
5 . The memory cell of claim 1 , wherein the memory cell comprises one ternary memory cell and one weight cell.
6 . The memory cell of claim 1 , wherein a number of transistors included in the weight cell is three, and a number of transistors included in the memory cell is nine.
7 . A memory device for a logic-in-memory, the memory device comprising:
a memory cell array in which a plurality of memory cells are arranged, each of the plurality of memory cells comprising a single ternary memory cell configured to store ternary data having a weight value of one of −1, 0 and +1 and a weight cell;
a decoder connected to the memory cell array via at least one word line and configured to select at least one of the plurality of memory cells; and
a read and write circuit connected to the memory cell array via a plurality of bit lines and configured to perform data latch,
wherein the weight cell is configured to control a current flowing in an operation line on a basis of a weight signal transmitted from the ternary memory cell and an activation signal transmitted via an activation line, and
the weight cell comprises a first transistor for receiving an input of weight data from a first node corresponding to a stored value of the ternary memory cell, a second transistor for receiving an input of inversed weight data from a second node corresponding to an inversed stored value of the ternary memory cell, and a third transistor for receiving an input of an activation signal transmitted via the activation line,
wherein when the ternary memory cell stores the weight value of −1, the weight data of the first node is 0 and the inversed weight data of the second node is 2,
when the ternary memory cell stores the weight value of 0, the weight data of the first node and the inversed weight data of the second node are 1, and
when the ternary memory cell stores the weight value of +1, the weight data of the first node is 2 and the inversed weight data of the second node is 0.
8 . The memory cell of claim 7 , wherein the first transistor is connected to the first node, the second transistor, and a first operation line,
the second transistor is connected to the second node, the first transistor, and a second operation line, and
the third transistor is connected to a third node that is a junction of the first transistor and the second transistor, and to the activation line.
9 . The memory cell of claim 8 , wherein the weight cell is configured to:
receive the weight data and the inversed weight data from the ternary memory cell;
receive the activation signal to activate the weight cell via the activation line; and
block at least one of a first current path along the first operation line and the first transistor or a second current path along the second operation line and the second transistor, on a basis of the weight data and the inversed weight data.
10 . The memory cell of claim 8 , wherein the plurality of memory cells are connected in parallel between the first operation line and the second operation line, and
a multiply and accumulate (MAC) operation is performed on a basis of a difference between a voltage applied to the first operation line and a voltage applied to the second operation line.