Amplifier having improved slew rate
Disclosed is an amplifier having a high slew rate without increasing power consumption. The amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, and a slew rate improvement circuit. Alternatively, the amplifier includes an input unit, a conversion unit, an amplification unit, a frequency compensation circuit, a first slew rate improvement circuit, and a second slew rate improvement circuit.
1. An amplifier comprising:
an input unit configured to receive a differential input signal at a first input terminal and a second input terminal, the input unit comprising a first input stage having a first AC ground node therein and a second input stage having a second AC ground node therein;
a conversion unit comprising a first current mirror comprising a first current determiner and a first current follower configured to operate in response to a voltage or current on a first current determination and/or voltage generation node of the first current determiner, a second current mirror comprising a second current determiner and a second current follower configured to operate in response to a voltage or current on a second current determination and/or voltage generation node of the second current determiner, a first transmission gate between the first current determiner and the second current determiner, and a second transmission gate between the first current follower and the second current follower, the conversion unit being configured to provide a first conversion voltage and a second conversion voltage that vary in response to the differential signal at the input unit;
an amplification unit configured to provide an output voltage in response to the first conversion voltage and the second conversion voltage;
a frequency compensation circuit comprising (i) a first compensation capacitor between an output terminal and the first current follower and (ii) a second compensation capacitor between the output terminal and the second current follower; and
a slew rate improvement circuit comprising a first slew rate improvement capacitor between the first current determination and/or voltage generation node and the first AC ground node and a second slew rate improvement capacitor between the second current determination and/or voltage generation node and the second AC ground node.
2. The amplifier according to claim 1 , wherein voltages on the first AC ground node and the second AC ground node increase and decrease in an amount equal to a respective increase and decrease in voltage at the first input terminal.
3. The amplifier according to claim 2 , wherein
voltages on the first current determination and/or voltage generation node and the second current determination and/or voltage generation node increase during a rising transition of the output voltage, and
the voltages on the first current determination and/or voltage generation node and the second current determination and/or voltage generation node decrease during a falling transition of the output voltage.
4. The amplifier according to claim 1 , wherein
the first current determiner comprises:
a seventh transistor having one terminal receiving a first supply voltage and another terminal connected to a first node; and
a ninth transistor having one terminal connected to the first node, a gate configured to receive a third bias voltage is applied, and another terminal connected to a gate of the seventh transistor and one terminal of the first transmission gate, wherein the other terminal of the ninth transistor is the first current determination and/or voltage generation node,
the first current follower comprises:
an eighth transistor having one terminal receiving the first supply voltage, another terminal connected to a second node, and a gate connected to the first current determination and/or voltage generation node; and
a tenth transistor having one terminal connected to the second node, a gate configured to receive the third bias voltage, and another terminal configured to provide the first conversion voltage and connected to one terminal of the second transmission gate, and
the second node is connected to one terminal of the first compensation capacitor.
5. The amplifier according to claim 4 , wherein
the second current determiner comprises:
an eleventh transistor having one terminal connected to another terminal of the first transmission gate and a gate configured to receive a fourth bias voltage, wherein the one terminal of the eleventh transistor is the second current determination and/or voltage generation node; and
a thirteenth transistor having one terminal connected to another terminal of the eleventh transistor, another terminal receiving a second supply voltage, and a gate connected to the second current determination and/or voltage generation node,
the second current follower comprises:
a twelfth transistor having one terminal, configured to provide the second conversion voltage, connected to another terminal of the second transmission gate, a gate configured to receive the fourth bias voltage, and another terminal connected to a fifth node; and
a fourteenth transistor having one terminal connected to the fifth node, a gate connected to the second current determination and/or voltage generation node, and another terminal receiving the second supply voltage, and
the fifth node is connected to one terminal of the second compensation capacitor.
6. The amplifier according to claim 5 , wherein
the first input stage comprises:
a first transistor having one terminal receiving the first supply voltage and a gate configured to receive a first bias voltage;
a fifth transistor having one terminal connected to another terminal of the first transistor, another terminal connected to the fourth node, and a gate connected to the second input terminal; and
a sixth transistor having one terminal connected to another terminal of the first transistor, another terminal connected to the fifth node, and a gate connected to the first input terminal, and
the first AC ground node is a common terminal of the first transistor, the fifth transistor, and the sixth transistor.
7. The amplifier according to claim 6 , wherein
the second input stage comprises:
a fourth transistor having one terminal receiving the second supply voltage, a gate configured to receive a second bias voltage, and another terminal connected to the second AC ground node;
a second transistor having one terminal connected to the first node, a gate connected to the second input terminal, and another terminal connected to the second AC ground node; and
a third transistor having one terminal connected to the second node, a gate connected to the first input terminal, and another terminal connected to the second AC ground node, and
the second AC ground node is a common terminal of the second transistor, the third transistor, and the fourth transistor.
8. The amplifier according to claim 5 , wherein
each of the first current determiner and the first current follower comprises a P-type transistor, and
each of the second current determiner and the second current follower comprises an N-type transistor.
9. The amplifier according to claim 7 , wherein
each of the first transistor to the third transistor comprises a P-type transistor, and
each of the fourth transistor to the sixth transistor comprises an N-type transistor.
10. An amplifier comprising:
an input unit configured to receive a differential input signal at a first input terminal and a second input terminal, the input unit comprising a first input stage having a first AC ground node therein and a second input stage having a second AC ground node therein;
a conversion unit comprising a first current mirror comprising a first current determiner and a first current follower configured to operate in response to a voltage or current on a first current determination and/or voltage generation node of the first current determiner, a second current mirror comprising a second current determiner and a second current follower configured to operate in response to a voltage or current on a second current determination and/or voltage generation node of the second current determiner, a first transmission gate between the first current determiner and the second current determiner, and a second transmission gate between the first current follower and the second current follower, the conversion unit being configured to provide a first conversion voltage and a second conversion voltage that vary in response to the differential signal at the input unit;
an amplification unit configured to provide an output voltage in response to the first conversion voltage and the second conversion voltage;
a frequency compensation circuit comprising (i) a first compensation capacitor between an output terminal and the first current follower and (ii) a second compensation capacitor between the output terminal and the second current follower;
a first slew rate improvement circuit comprising a switching element configured to reversibly connect each of a first terminal configured to output the first conversion voltage and a second terminal configured to output the second conversion voltage to the output terminal for a predetermined time during which the output voltage transitions in response to the input voltage at the first input terminal; and
a second slew rate improvement circuit comprising a first slew rate improvement capacitor between the first current determination and/or voltage generation node and the first AC ground node and a second slew rate improvement capacitor between the second current determination and/or voltage generation node and the second AC ground node.
11. The amplifier according to claim 10 , wherein voltages on the first AC ground node and the second AC ground node increase and decrease in an amount equal to a respective increase and decrease in voltage at the first input terminal.
12. The amplifier according to claim 11 , wherein
voltages on the first current determination and/or voltage generation node and the second current determination and/or voltage generation node increase during a rising transition of the output voltage, and
the voltages on the first current determination and/or voltage generation node and the second current determination and/or voltage generation node decrease in a falling transition of the output voltage.
13. The amplifier according to claim 10 , wherein
the first current determiner comprises:
a seventh transistor having one terminal receiving a first supply voltage and another terminal connected to a first node; and
a ninth transistor having one terminal connected to the first node, a gate configured to receive a third bias voltage, and another terminal connected to a gate of the seventh transistor and one terminal of the first transmission gate, wherein the other terminal of the ninth transistor is the first current determination and/or voltage generation node,
the first current follower comprises:
an eighth transistor having one terminal receiving the first supply voltage, another terminal connected to a second node, and a gate connected to the first current determination and/or voltage generation node; and
a tenth transistor having one terminal connected to the second node, a gate configured to receive the third bias voltage, and another terminal configured to provide the first conversion voltage and connected to one terminal of the second transmission gate, and
the second node is connected to one terminal of the first compensation capacitor.
14. The amplifier according to claim 13 , wherein
the second current determiner comprises:
an eleventh transistor having one terminal connected to another terminal of the first transmission gate and a gate configured to receive a fourth bias voltage, wherein the one terminal of the eleventh transistor is the second current determination and/or voltage generation node; and
a thirteenth transistor having one terminal connected to another terminal of the eleventh transistor, another terminal receiving a second supply voltage, and a gate connected to the second current determination and/or voltage generation node,
the second current follower comprises:
a twelfth transistor having one terminal, configured to provide the second conversion voltage, connected to another terminal of the second transmission gate, a gate configured to receive the fourth bias voltage, and another terminal connected to a fifth node; and
a fourteenth transistor having one terminal connected to the fifth node, a gate connected to the second current determination and/or voltage generation node, and another terminal receiving the second supply voltage, and
the fifth node is connected to one terminal of the second compensation capacitor.
15. The amplifier according to claim 14 , wherein
the first input stage comprises:
a first transistor having one terminal receiving the first supply voltage and a gate configured to receive a first bias voltage;
a fifth transistor having one terminal connected to another terminal of the first transistor, another terminal connected to the fourth node, and a gate connected to the second input terminal; and
a sixth transistor having one terminal connected to another terminal of the first transistor, another terminal connected to the fifth node, and a gate connected to the first input terminal, and
the first AC ground node is a common terminal of the first transistor, the fifth transistor, and the sixth transistor.
16. The amplifier according to claim 15 , wherein
the second input stage comprises:
a fourth transistor having one terminal receiving the second supply voltage, a gate configured to receive a second bias voltage, and another terminal connected to the second AC ground node;
a second transistor having one terminal connected to the first node, a gate connected to the second input terminal, and another terminal connected to the second AC ground node; and
a third transistor having one terminal connected to the second node, a gate connected to the first input terminal, and another terminal connected to the second AC ground node, and
the second AC ground node is a common terminal of the second transistor, the third transistor, and the fourth transistor.
17. The amplifier according to claim 14 , wherein
each of the first current determiner and the first current follower comprises a P-type transistor, and
each of the second current determiner and the second current follower comprises an N-type transistor.
18. The amplifier according to claim 16 , wherein
each of the first transistor to the third transistor comprises a P-type transistor, and
each of the fourth transistor to the sixth transistor comprises an N-type transistor.
19. The amplifier according to claim 10 , wherein the first slew rate improvement circuit comprises:
a seventeenth transistor having one terminal to which the first conversion voltage is applied, another terminal connected to the output terminal, and a gate configured to receive a first input voltage; and
an eighteenth transistor having one terminal configured to receive the second conversion voltage, another terminal connected to the output terminal, and a gate configured to receive the first input voltage.
20. A source driver circuit using a buffer implemented by connecting the output terminal of the amplifier according to claim 1 to the second input terminal.