Block or page lock features in serial interface memory
Embodiments are provided for protecting boot block space in a memory device. Such a memory device may include a memory array having a protected portion and a serial interface controller. The memory device may have a register that enables or disables access to the portion when data indicating whether to enable or disable access to the portion is written into the register via a serial data in (SI) input.
1. A memory device, comprising:
a memory array;
a serial interface controller configured to interface with a master device;
a register coupled to the serial interface controller, wherein the register is configured receive a password from the master device via the serial interface controller and store the password received from the master device as a received password, wherein read access to at least a portion of the memory array is enabled if the received password is validated via comparison of the received password with a stored value; and
a second register coupled to the serial interface controller, wherein the second register when in operation stores an indication of whether to enable or prevent write or erase access to the portion of the memory array, wherein alteration of the indication is permitted only subsequent to validation of the received password via the comparison of the received password with the stored value.
2. The memory device of claim 1 , wherein the at least a portion of the memory array comprises a boot block space of the memory array.
3. The memory device of claim 1 , wherein the at least a portion of the memory array comprises a non-boot block space of the memory array.
4. The memory device of claim 1 , wherein the at least a portion of the memory array comprises an entirety of the memory array.
5. The memory device of claim 1 , wherein the at least a portion of the memory array comprises an individual page within a particular block of the memory array.
6. The memory device of claim 1 , wherein the at least a portion of the memory array comprises a block region comprising one or more blocks of the memory array.
7. The memory device of claim 6 , wherein the block region is user-definable.
8. The memory device of claim 6 , wherein the block region comprises an entire boot area.
9. The memory device of claim 1 , wherein the master device is configured to initiate a read operation as the access.
10. The memory device of claim 1 , wherein the master device is configured to initiate a write operation as the access.
11. The memory device of claim 1 , wherein the master device is configured to initiate an erase operation as the access.
12. The memory device of claim 1 , wherein the serial interface controller is configured to initiate the access of the at least a portion of the memory array subsequent to receipt of a command when the received password is validated via comparison of the received password with the stored value.
13. The memory device of claim 1 , wherein the serial interface controller is configured to translate signals sent to the memory array into command latch enable (CLE), address latch enable (ALE), write enable (WE), and read enable (RE) signals.
14. The memory device of claim 1 , wherein the memory device is configured to track a number of unsuccessful attempts in which the master device attempts to access the at least a portion of the memory array and prevent further accesses to the portion of the memory array when the number of unsuccessful attempts reaches a threshold value.
15. The memory device of claim 1 , wherein the memory device is configured to authenticate the master device responsive to comparing the received password with the stored value to validate the received password.
16. The memory device of claim 1 , wherein the memory array is configured to store the stored value.
17. A system, comprising:
a master device; and
a memory device coupled to the master device, wherein the memory device comprises:
a memory array;
a serial interface controller, wherein the serial interface controller is configured to interface with the master device to receive a password from the master device;
a register coupled to the serial interface controller, wherein the register is configured receive the password from the master device via the serial interface controller and store the password received from the master device as a received password, wherein the memory device is configured to enable read access to at least a portion of the memory array if the received password is validated via comparison of the received password with a stored value; and
a second register coupled to the serial interface controller, wherein the second register when in operation stores an indication of whether to enable or prevent write or erase access to the portion of the memory array, wherein alteration of the indication by the master device is permitted only subsequent to validation of the received password via the comparison of the received password with the stored value.
18. The system of claim 17 , comprising a second memory device coupled to the master device.
19. The system of claim 17 , wherein the memory device comprises a NAND memory device.
20. A method, comprising:
receiving a password at an input of a serial interface controller of a device;
writing the password to a first portion of the device;
evaluating the password to determine whether the password is validated via comparison of the password with a previously stored value in a second portion of the device;
enabling read access to at least a portion of a memory array of the device when the password is validated;
receiving a write or erase access to the at least a portion of the memory array;
preventing the write or erase access to the at least a portion of the memory when an indication stored in a register of the device has a first value;
receiving an access to alter the indication stored in the register to a second value; and
altering the indication stored in the register to a second value only if the password has been validated.