Low-voltage fuse read circuit
Circuits and methods for reading fusible links that allows use of low-voltage logic circuitry utilizing devices that may have a high-voltage stand-off capability. Embodiments provide predictable operation that is less susceptible to PVT variations, allow the use of arrays of fuses that may be scaled to relatively large memory sizes, uses little integrated circuit area, and do not require extra pins for operation. Embodiments utilize a latch circuit and voltage dividers to generate a reference voltage V REF and a fuse voltage V FUSE , and then compares and latches the greater of those voltages. The circuitry does not require any more supply voltage than is needed to turn ON input pass transistors to the latch at a slightly higher voltage (V TH ) than V REF . Since V REF may be about 0.1V, that turn-ON voltage may be as low as about 0.1V+V TH , and thus would be less than a V DD_MIN of about 1V.
1. A fuse reading circuit including:
(a) a set of one or more fuses;
(b) a first circuit configured to generate a reference voltage as a function of the resistance of a reference resistor and of a first bias resistor;
(c) a second circuit configured to generate a testable fuse voltage as a function of the resistance of a selected fuse from the set of one or more fuses and of a second bias resistor;
(d) a latch circuit having a first input selectively couplable to the reference voltage through a first pass switch, a second input selectively couplable to the testable fuse voltage through a second pass switch, and at least one output having a first state if the reference voltage is greater than the testable fuse voltage, and a second state if the reference voltage is less than the testable fuse voltage.
2. The fuse reading circuit of claim 1 , wherein the reference resistor and the first bias resistor are configured as a voltage divider.
3. The fuse reading circuit of claim 1 , wherein the resistance of the selected fuse and the second bias resistor are configured as a voltage divider.
4. The fuse reading circuit of claim 1 , wherein the first bias resistor and the second bias resistor have variable resistance values.
5. The fuse reading circuit of claim 1 , wherein the first bias resistor and the second bias resistor have approximately the same resistances.
6. The fuse reading circuit of claim 1 , wherein the reference resistor has a variable resistance value.
7. The fuse reading circuit of claim 1 , wherein the latch circuit may be selectively enabled or disabled in response to a control signal.
8. The fuse reading circuit of claim 1 , wherein the first and second pass switches are field effect transistors having a gate, and wherein the gates of the field effect transistors are coupled to a control signal that enables coupling of the reference voltage and the testable fuse voltage to the respective first and second inputs of the latch circuit.
9. The fuse reading circuit of claim 1 , wherein the latch circuit includes:
(a) a first and second field effect transistors having conduction channels coupled in series, each of the first and second field effect transistors having respective gates; and
(b) a third and fourth field effect transistors having conduction channels coupled in series, each of the third and fourth field effect transistors having respective gates;
wherein the gates of the first and second field effect transistors are coupled to the conduction channels of the third and fourth field effect transistors, and the gates of the third and fourth field effect transistors are coupled to the conduction channels of the first and second field effect transistors.
10. The fuse reading circuit of claim 9 , wherein the conduction channels of the first and second field effect transistors are selectively couplable to the reference voltage through the first pass switch and the conduction channels of the third and fourth field effect transistors are selectively couplable to the testable fuse voltage through the second pass switch.
11. The fuse reading circuit of claim 10 , wherein the first and second pass switches are field effect transistors having a gate, and wherein the gates of the field effect transistors are coupled to a control signal that enables coupling of the reference voltage and the testable fuse voltage to the respective first and second inputs of the latch circuit.
12. The fuse reading circuit of claim 1 , wherein the latch circuit includes first and second outputs each indicating the relative voltages of the reference voltage and the testable fuse voltage, and further including an output validation circuit coupled to the first and second outputs of the latch circuit and configured to validate that the first and second outputs are in complementary states.
13. A fuse reading circuit including:
(a) a set of one or more fuses;
(b) a first circuit configured to generate a reference voltage as a function of the resistance of a reference resistor and of a first bias resistor;
(c) a second circuit configured to generate a testable fuse voltage as a function of the resistance of a selected fuse from the set of one or more fuses and of a second bias resistor;
(d) a latch circuit having a first input selectively couplable to the reference voltage, a second input selectively couplable to the testable fuse voltage, and at least one output having a first state if the reference voltage is greater than the testable fuse voltage, and a second state if the reference voltage is less than the testable fuse voltage; and
(e) a charge storage capacitor coupled to at least one of the first and second inputs of the latch circuit.
14. The fuse reading circuit of claim 13 , wherein the latch circuit includes:
(a) a first and second field effect transistors having conduction channels coupled in series, each of the first and second field effect transistors having respective gates; and
(b) a third and fourth field effect transistors having conduction channels coupled in series, each of the third and fourth field effect transistors having respective gates;
wherein the gates of the first and second field effect transistors are coupled to the conduction channels of the third and fourth field effect transistors, and the gates of the third and fourth field effect transistors are coupled to the conduction channels of the first and second field effect transistors.
15. The fuse reading circuit of claim 14 , wherein the conduction channels of the first and second field effect transistors are selectively couplable to the reference voltage through the first pass switch and the conduction channels of the third and fourth field effect transistors are selectively couplable to the testable fuse voltage through the second pass switch.
16. The fuse reading circuit of claim 13 , wherein the latch circuit includes first and second outputs each indicating the relative voltages of the reference voltage and the testable fuse voltage, and further including an output validation circuit coupled to the first and second outputs of the latch circuit and configured to validate that the first and second outputs are in complementary states.
17. A fuse reading circuit including:
(a) a set of one or more fuses;
(b) a first circuit configured to generate a reference voltage as a function of the resistance of a reference resistor and of a first bias resistor;
(c) a second circuit configured to generate a testable fuse voltage as a function of the resistance of a selected fuse from the set of one or more fuses and of a second bias resistor;
(d) a latch circuit having a first input selectively couplable to the reference voltage, a second input selectively couplable to the testable fuse voltage, and at least one output having a first state if the reference voltage is greater than the testable fuse voltage, and a second state if the reference voltage is less than the testable fuse voltage; and
(e) a capacitor coupled to the reference voltage.
18. The fuse reading circuit of claim 17 , wherein the latch circuit includes:
(a) a first and second field effect transistors having conduction channels coupled in series, each of the first and second field effect transistors having respective gates; and
(b) a third and fourth field effect transistors having conduction channels coupled in series, each of the third and fourth field effect transistors having respective gates;
wherein the gates of the first and second field effect transistors are coupled to the conduction channels of the third and fourth field effect transistors, and the gates of the third and fourth field effect transistors are coupled to the conduction channels of the first and second field effect transistors.
19. The fuse reading circuit of claim 18 , wherein the conduction channels of the first and second field effect transistors are selectively couplable to the reference voltage through the first pass switch and the conduction channels of the third and fourth field effect transistors are selectively couplable to the testable fuse voltage through the second pass switch.
20. The fuse reading circuit of claim 17 , wherein the latch circuit includes first and second outputs each indicating the relative voltages of the reference voltage and the testable fuse voltage, and further including an output validation circuit coupled to the first and second outputs of the latch circuit and configured to validate that the first and second outputs are in complementary states.