Microcontroller interface for audio signal processing

1. A processing system comprising:

a special-purpose host processor operable as a stand-alone host processor;

a co-processor including an artificial neural network;

a communications interface between the stand-alone host processor and the co-processor configured to transmit information therebetween;

wherein the co-processor is configured to provide a frequency mask to the special-purpose host processor over the communications interface, wherein the frequency mask is a set of attenuation or amplification factors corresponding to a set of frequencies to be suppressed or boosted for each of a number of time steps of an audio sample; and

wherein the special-purpose host processor is a hearing-aid processor configured to transmit frequency elements or signal spectrum information to the co-processor in the form of Fourier transforms over the communications interface.

2. The system of claim 1 , wherein the communications interface between the stand-alone host processor and the co-processor is a serial peripheral interface (“SPI”) bus or inter-integrated circuit (“I 2 C”) bus.

3. The system of claim 1 , wherein the co-processor is configured to enhance the special-purpose processing of the hearing-aid processor by providing information to the hearing-aid processor over the communications interface, thereby enabling the hearing-aid processor to selectively suppress noise and enhance desired signals.

4. The system of claim 1 , wherein the co-processor further includes a demultiplexer configured to demultiplex serial signals from the communications interface into parallel signals for a plurality of inputs of the artificial neural network.

5. The system of claim 1 , wherein the artificial neural network is disposed in an analog multiplier array of a plurality of two-quadrant multipliers in a memory sector of the system.

6. The system of claim 1 , wherein synaptic weights of the artificial neural network are stored in firmware of the co-processor, and wherein the firmware is configured for cloud-based updates to update the synaptic weights of the artificial neural network.

7. The system of claim 1 , wherein the stand-alone host processor and the co-processor are embodied in a single monolithic integrated circuit, a stacked die assembly, a multi-chip module, or separate integrated circuits of separate modules.

8. The system of claim 1 , wherein the system is configured to operate on battery power.

9. A processor, comprising:

one or more interface circuits comprising a demultiplexer configured to demultiplex serial signals into parallel signals;

wherein the serial signals are received from a serial communications interface between the processor and a special-purpose host processor;

wherein the special-purpose host processor is a hearing-aid processor;

a multi-layered artificial neural network configured to receive the parallel signals from the interface circuits;

wherein the processor is configured to provide a frequency mask to the hearing-aid processor over the serial communications interface, wherein the frequency mask is a set of attenuation or amplification factors corresponding to a set of frequencies to be suppressed or boosted for each of a number of time steps of an audio sample; and

wherein the processor is further configured to receive frequency elements or signal spectrum information from the hearing-aid processor in the form of Fourier transforms over the serial communications interface.

10. The processor of claim 9 , wherein the processor is configured to enhance the special-purpose processing of the hearing-aid processor by providing information to the hearing-aid processor over the serial communications interface, thereby enabling the hearing-aid processor to selectively suppress noise and enhance desired signals.

11. The processor of claim 9 , by providing the frequency mask to the hearing-aid processor, the processor indicates noise frequencies to suppress and signal frequencies to boost.

12. The processor of claim 9 , wherein the artificial neural network is disposed in an analog multiplier array of a plurality of two-quadrant multipliers in a memory sector of the processor.

13. The processor of claim 9 , wherein the serial communications interface between the special-purpose host processor and the co-processor is a serial peripheral interface (“SPI”) bus or inter-integrated circuit (“I 2 C”) bus.

14. The processor of claim 9 ,

wherein synaptic weights of the artificial neural network are stored in firmware of the co-processor, and

wherein the firmware is configured for cloud-based updates to update the synaptic weights of the artificial neural network.

15. The processor of claim 9 , wherein the special-purpose host processor and the co-processor are embodied in a single monolithic integrated circuit, a stacked die assembly, a multi-chip module, or separate integrated circuits of separate modules.

16. The processor of claim 9 , wherein the processor and the special-purpose host processor are configured to operate on battery power.

17. A method of a processing system having a special-purpose host processor configured as a hearing-aid processor and a co-processor, comprising:

enhancing special-purpose processing of the hearing-aid processor with an artificial neural network of the co-processor by providing information to the hearing-aid processor over a communications interface, thereby enabling the hearing-aid processor to selectively suppress noise and enhance desired signals;

transmitting a frequency mask from the co-processor to the special-purpose host processor over a communications interface, wherein the frequency mask is a set of attenuation or amplification factors corresponding to a set of frequencies to be suppressed or boosted for each of a number of time steps of an audio sample;

transmitting frequency elements or signal spectrum information from the special-purpose host processor to the co-processor in the form of Fourier transforms over a serial communications interface; and

demultiplexing serial signals from the serial communications interface with a demultiplexer of the co-processor into parallel signals for a plurality of inputs of the artificial neural network.