Extending fused multiply-add instructions
Extending fused multiply-add instructions, including: receiving an extended fused multiply-add (FMA) instruction comprising a first subset of bits indicating a corresponding register for each operand of a fused multiply-add (FMA) operation and a second subset of bits indicating a different register storing data describing one or more transformations applicable to one or more operands of the FMA operation; and performing, based on the extended FMA instruction.
1. A method of extending fused multiply-add instructions, the method comprising:
receiving an extended fused multiply-add (FMA) instruction comprising: a first subset of bits indicating a corresponding register for each operand of a fused multiply-add (FMA) operation, and a second subset of bits comprising an opcode for the extended FMA instruction, wherein the opcode identifies extended FMA instruction from an instruction set of a plurality of extended FMA instructions each having a different predefined opcode corresponding to a different combination of transformation-operand groupings; and
performing, based on the opcode of the extended FMA instruction, the one or more transformations and the FMA operation.
2. The method of claim 1 , wherein the one or more transformations comprise a bit masking transformation.
3. The method of claim 1 , wherein the one or more transformations comprise a bit shifting operation.
4. The method of claim 1 , wherein the one or more transformations comprises a rounding operation.
5. The method of claim 1 , wherein the one or more transformations comprises a casting operation.
6. The method of claim 1 , wherein the one or more transformations comprises a conditional zeroing operation.
7. An apparatus for extending fused multiply-add instructions, the apparatus configured to perform steps comprising:
receiving an extended fused multiply-add (FMA) instruction comprising: a first subset of bits indicating a corresponding register for each operand of a fused multiply-add (FMA) operation, and a second subset of bits comprising an opcode for the extended FMA instruction, wherein the opcode identifies extended FMA instruction from an instruction set of a plurality of extended FMA instructions each having a different predefined opcode corresponding to a different combination of transformation-operand groupings; and
performing, based on the opcode of the extended FMA instruction, the one or more transformations and the FMA operation.
8. The apparatus of claim 7 , wherein the one or more transformations comprise a bit masking transformation.
9. The apparatus of claim 7 , wherein the one or more transformations comprise a bit shifting operation.
10. The apparatus of claim 7 , wherein the one or more transformations comprises a rounding operation.
11. Apparatus of claim 7 , wherein the one or more transformations comprises a casting operation.
12. The apparatus of claim 7 , wherein the one or more transformations comprises a conditional zeroing operation.
13. A computer program product disposed upon a non-transitory computer readable medium, the computer program product comprising computer program instructions for extending fused multiply-add instructions that, when executed, cause a computer system to perform steps comprising:
receiving an extended fused multiply-add (FMA) instruction comprising: a first subset of bits indicating a corresponding register for each operand of a fused multiply-add (FMA) operation, and a second subset of bits comprising an opcode for the extended FMA instruction, wherein the opcode identifies extended FMA instruction from an instruction set of a plurality of extended FMA instructions each having a different predefined opcode corresponding to a different combination of transformation-operand groupings; and
performing, based on the opcode of the extended FMA instruction, the one or more transformations and the FMA operation.
14. The computer program product of claim 13 , wherein the one or more transformations comprise a bit masking transformation.
15. The computer program product of claim 13 , wherein the one or more transformations comprise a bit shifting operation.
16. The computer program product of claim 13 , wherein the one or more transformations comprises a rounding operation.
17. Computer program product of claim 13 , wherein the one or more transformations comprises a casting operation.
18. The computer program product of claim 13 , wherein the one or more transformations comprises a conditional zeroing operation.