Asynchronous power loss impacted data structure

1. A system comprising:

a storage system comprising control circuitry and a memory array having multiple groups of memory cells,

wherein the control circuitry is configured to maintain a relationship between a logical block address (LBA) and a physical address (PA) of data stored on the memory array in a logical-to-physical (L2P) data structure and store a synchronization point indicating a specific point where data operations on the memory array are complete and the L2P data is updated and stored, and

wherein the control circuitry, when resuming operation from a low-power state, is configured to:

determine an error rate of one or more groups of memory cells programmed or erased subsequent to the synchronization point;

relocate groups of memory cells having an error rate above a stable threshold;

rebuild the L2P data structure subsequent to relocating the groups of memory cells having the error rate above the stable threshold;

update the synchronization point subsequent to rebuilding the L2P data structure; and

transition from resuming operation from the low-power state to in operation subsequent to updating the synchronization point,

wherein the stable threshold is below and separate from a maximum error threshold, wherein the maximum error threshold is a threshold above which the system is not configured to correct errors in the group of memory cells.

2. The system of claim 1 ,

wherein resuming operation from the low-power state comprises resuming operation from an asynchronous power loss (APL), and

wherein, to rebuild the L2P data structure comprises to rebuild the L2P data structure in response to the APL.

3. The system of claim 1 ,

wherein the control circuitry is configured to determine the last written group of memory cells in the group data structure programmed before resuming operation from the low power state, and

wherein to determine the error rate of one or more groups of memory cells programmed or erased subsequent to the synchronization point comprises:

to determine an error rate of the last written group of memory cells in the group data structure.

4. The system of claim 3 ,

wherein, in response to determining that the error rate of the last written group of memory cells is above the stable threshold, the control circuitry is configured to:

relocate the last written group of memory cells; and

rebuild the L2P data structure subsequent to relocating the last written group of memory cells.

5. The system of claim 4 ,

wherein, in response to determining that the error rate of the last written group of memory cells is above the stable threshold, the control circuitry is configured to:

mark all groups of memory cells programmed or erased between the synchronization point and the last group of memory cells programmed before resuming operation from the low-power state as valid in a group data structure.

6. The system of claim 5 ,

wherein the control circuitry is configured to mark all groups of memory cells programmed or erased between the synchronization point and the last group of memory cells programmed before resuming operation from the low-power state as valid prior to rebuilding the L2P data structure.

7. The system of claim 4 ,

wherein, in response to determining that the error rate of the last written group of memory cells is above the stable threshold, the control circuitry is configured to:

update the synchronization point subsequent to rebuilding the L2P data structure; and

transition from resuming operation from the low-power state to in operation subsequent to updating the synchronization point.

8. The system of claim 1 , wherein a group of memory cells comprises a page of memory cells.

9. The system of claim 1 , wherein the stable threshold is between 20% and 50% below the maximum error threshold.

10. A system comprising:

a storage system comprising control circuitry and a memory array having multiple groups of memory cells,

wherein the control circuitry is configured to maintain a relationship between a logical block address (LBA) and a physical address (PA) of data stored on the memory array in a logical-to-physical (L2P) data structure and store a synchronization point indicating a specific point where data operations on the memory array are complete and the L2P data is updated and stored, and

wherein the control circuitry, when resuming operation from a low-power state, is configured to:

determine if the last group of memory cells programmed before resuming operation from the low-power state is the synchronization point; and

in response to determining that the last group of memory cells programmed before resuming operation from the low-power state is not the synchronization point:

determine an error rate of the last group of memory cells programmed before resuming operation from the low-power state; and

if the error rate of the last group of memory cells programmed before resuming operation from the low-power state is below a threshold:

rebuild the L2P data structure;

update the synchronization point subsequent to rebuilding the L2P data structure; and

transition from resuming operation from the low-power state to in operation subsequent to updating the synchronization point,

wherein the stable threshold is below and separate from a maximum error threshold, wherein the maximum error threshold is a threshold above which the system is not configured to correct errors in the group of memory cells.

11. The system of claim 10 ,

wherein, if the error rate of the last group of memory cells programmed before resuming operation from the low power state is below the threshold, the control circuitry is configured to:

mark all groups of memory cells programmed or erased between the synchronization point and the last group of memory cells programmed before resuming operation from the low-power state as valid in a group data structure.

12. The system of claim 11 ,

wherein the control circuitry is configured to mark all groups of memory cells programmed or erased between the synchronization point and the last group of memory cells programmed before resuming operation from the low-power state as valid prior to rebuilding the L2P data structure.

13. The system of claim 10 ,

wherein resuming operation from the low-power state comprises resuming operation from an asynchronous power loss (APL), and

wherein, to rebuild the L2P data structure comprises to rebuild the L2P data structure in response to the APL.

14. The system of claim 10 , wherein a group of memory cells comprises a page of memory cells.

15. The system of claim 10 , wherein the stable threshold is between 20% and 50% below the maximum error threshold.

16. A method comprising:

maintaining, using control circuitry of a storage system comprising a memory array having multiple groups of memory cells:

a relationship between a logical block address (LBA) and a physical address (PA) of data stored on a memory array of the storage system in a logical-to-physical (L2P) data structure; and

a synchronization point indicating a specific point where data operations on the memory array are complete and the L2P data is updated and stored; and

determining, using the control circuitry when resuming operation from a low-power state, an error rate of one or more groups of memory cells of the memory array programmed or erased subsequent to the synchronization point;

in response to determining that the error rate of the one or more groups of memory cells are above the stable threshold, using the control circuitry:

relocating groups of memory cells having an error rate above a stable threshold;

rebuilding the L2P data structure subsequent to relocating the groups of memory cells having the error rate above the stable threshold;

updating the synchronization point subsequent to rebuilding the L2P data structure; and

transitioning from resuming operation from the low-power state to in operation subsequent to updating the synchronization point,

wherein the stable threshold is below and separate from a maximum error threshold, wherein the maximum error threshold is a threshold above which the system is not configured to correct errors in the group of memory cells.

17. The method of claim 16 ,

wherein resuming operation from the low-power state comprises resuming operation from an asynchronous power loss (APL), and

wherein rebuilding the L2P data structure comprises in response to the APL.

18. The method of claim 16 , comprising:

determining, using the control circuitry, the last written group of memory cells in the group data structure programmed before resuming operation from the low power state,

wherein determining the error rate of the one or more groups of memory cells programmed or erased subsequent to the synchronization point comprises:

determining an error rate of the last written group of memory cells in the group data structure; and

in response to determining that the error rate of the last written group of memory cells is above the stable threshold:

marking all groups of memory cells programmed or erased between the synchronization point and the last group of memory cells programmed before resuming operation from the low-power state as valid in a group data structure;

relocating the last written group of memory cells; and

rebuilding the L2P data structure subsequent to relocating the last written group of memory cells;

update the synchronization point subsequent to rebuilding the L2P data structure; and

transition from resuming operation from the low-power state to in operation subsequent to updating the synchronization point.

19. The method of claim 16 , wherein the stable threshold is between 20% and 50% below the maximum error threshold.

20. The method of claim 16 , wherein a group of memory cells comprises a page of memory cells.