Method and structure for high performance resonance circuit with single crystal piezoelectric capacitor dielectric material
A method and structure for single crystal acoustic electronic device. The device includes a substrate having an enhancement layer formed overlying its surface region, a support layer formed overlying the enhancement layer, and an air cavity formed through a portion of the support layer. Single crystal piezoelectric material is formed overlying the air cavity and a portion of the enhancement layer. Also, a first electrode material coupled to the backside surface region of the crystal piezoelectric material and spatially configured within the cavity. A second electrode material is formed overlying the topside of the piezoelectric material, and a dielectric layer formed overlying the second electrode material. Further, one or more shunt layers can be formed around the perimeter of a resonator region of the device to connect the piezoelectric material to the enhancement layer.
1. A method for fabricating an acoustic resonator device, the method comprising:
forming a piezoelectric film overlying a growth substrate;
forming a first electrode overlying the piezoelectric film;
forming a first passivation layer overlying the first electrode and the piezoelectric film;
forming a support layer overlying the first passivation layer, the first electrode, and the piezoelectric film thereby forming a device on the growth substrate;
polishing the support layer;
etching the support layer to form an air cavity;
forming a bonding support layer overlying a bond substrate;
flipping the device on the growth substrate and bonding the polished support layer to the bonding support layer with the air cavity between the device on the growth substrate and the bonding support layer thereby forming a bonded device;
removing the growth substrate from the bonded device;
forming an electrode contact via within the piezoelectric film overlying the first electrode on the bonded device;
forming a second electrode layer overlying the piezoelectric film and within the contact via;
etching the second electrode layer to form a top metal separated from a second electrode, wherein the top metal is physically coupled to the first electrode through the electrode contact via and the second electrode is overlying the piezoelectric film;
forming a first contact metal overlying the second electrode and the piezoelectric film;
forming a second contact metal overlying the top metal and the piezoelectric film; and
forming a second passivation layer overlying the piezoelectric film, the second electrode, and the top metal;
wherein the second passivation layer is characterized by a consistent thickness.
2. The method of claim 1 wherein the growth substrate and bond substrate includes silicon (S), silicon carbide (SiC), sapphire (Al2O3), or silicon dioxide (SiO2).
3. The method of claim 1 wherein the piezoelectric film is a single crystal or polycrystalline piezoelectric film that includes aluminum nitride (AlN), gallium nitride (GaN), AlxGa1−xN alloys, or other epitaxial materials; or
wherein the piezoelectric film is an upper portion of a polycrystalline piezoelectric film that includes aluminum nitride (AlN), gallium nitride (GaN), AlxGa1−xN alloys, or other polycrystalline epitaxial materials.
4. The method of claim 1 wherein the first passivation layer or the second passivation layer is characterized by a thickness of about 50 nm to about 100 nm.
5. The method of claim 1 wherein the first electrode, second electrode, and top metal can include molybdenum (Mo), ruthenium (Ru), tungsten (W), or other conductive materials, wherein the first and second passivation layers can include silicon nitride (SiN), silicon oxide (SiO), or silicon dioxide (SiO2).
6. The method of claim 1 wherein the first and second contact metals include gold (Au), aluminum (Al), copper (Cu), nickel (Ni), aluminum bronze (AlCu), or alloys of these materials.
7. The method of claim 1 wherein polishing the support layer includes a chemical-mechanical planarization (CMP) process; wherein the support layer and the bonding support layer include silicon dioxide (SiO2); and wherein removing the growth substrate includes a grinding process, a blanket etching process, a film transfer process, an ion implantation transfer process, or a laser crack transfer process.
8. The method of claim 1 further comprising processing the second electrode and the top metal to form a processed second electrode and a processed top metal, wherein the processed second electrode includes an energy confinement structure.
9. The method of claim 1 further comprising processing the first electrode to form a processed first electrode, wherein the processed first electrode includes an energy confinement structure.
10. The method of claim 1 further comprising processing the second electrode and the top metal to form a processed second electrode and a processed top metal, wherein the processed second electrode includes an energy confinement structure; and further comprising processing the first electrode to form a processed first electrode, wherein the processed first electrode includes an energy confinement structure.