IP Library Granted Patent US 12,156,480
Granted Patent B2
US 12,156,480 · App. 17/695,844 · Granted Nov 26, 2024

Semiconductor device and manufacturing method thereof

Inventor: Takaaki Hioka (Tokyo, JP)
Assignee: ABLIC Inc.
H10N52/101G01R33/077H10N52/01
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Quick Facts
Patent No.
US 12,156,480
App. No.
17/695,844
Granted
Nov 26, 2024
Kind
B2
Abstract

A semiconductor device includes a semiconductor substrate of a first conductivity type, and a vertical Hall element provided on the semiconductor substrate. The vertical Hall element includes an impurity diffusion layer of a second conductivity type and three or more electrodes. The impurity diffusion layer is provided on the semiconductor substrate and has an impurity concentration which increases as a depth increases. The three or more electrodes are provided in a straight line on a surface of the impurity diffusion layer and are composed of an impurity region of the second conductivity type having a higher concentration than the impurity diffusion layer.

Claims (15)

1. A semiconductor device comprising:

a semiconductor substrate of a first conductivity type; and

a vertical Hall element provided on the semiconductor substrate,

wherein the vertical Hall element comprises:

an impurity diffusion layer of a second conductivity type, provided on the semiconductor substrate and having an impurity concentration which increases as a depth increases, wherein the impurity concentration at an interface between the impurity diffusion layer and the semiconductor substrate is equal to or higher than an impurity concentration of the semiconductor substrate; and

three or more electrodes provided in a straight line directly on a surface of the impurity diffusion layer and composed of an impurity region of the second conductivity type having a higher concentration than that of the impurity diffusion layer,

wherein the impurity concentration of the impurity diffusion layer has a constant concentration in an upper part of the impurity diffusion layer and increases as the depth increases from a predetermined depth.

2. The semiconductor device according to claim 1 , wherein the impurity concentration of the impurity diffusion layer has a peak concentration and decreases as the depth increases from a depth having the peak concentration.

3. The semiconductor device according to claim 1 , further comprising an insulating film provided around the electrodes at the surface of the impurity diffusion layer and having a bottom located deeper than bottom surfaces of the electrodes with respect to the surface.

4. The semiconductor device according to claim 1 , wherein the electrodes provided in a straight line on the surface of the impurity diffusion layer are three electrodes,

a drive current is passed between the electrodes located at two ends, and

a Hall voltage is detected by the electrode located at a center.

5. The semiconductor device according to claim 1 , wherein the electrodes provided in a straight line on the surface of the impurity diffusion layer are five electrodes,

a drive current is passed from the electrode located at a center toward the electrodes located at two ends, and

a Hall voltage between two electrodes located between the electrode located at the center and the electrodes located at the two ends is detected.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 17, 2022
From: HIOKA, TAKAAKI
To: ABLIC INC.
Reel/Frame 059300/0200 →