Envelope tracking voltage correction in a transmission circuit
Envelope tracking (ET) voltage correction in a transmission circuit is provided. The transmission circuit includes a transceiver circuit and a power amplifier circuit(s). The transceiver circuit generates a radio frequency (RF) signal(s) from a time-variant modulation vector and the power amplifier circuit(s) amplifies the RF signal(s) based on a modulated voltage and provides the amplified RF signal(s) to a coupled RF front-end circuit. Herein, the transceiver circuit is configured to apply a complex filter(s) to the time-variant modulation vector and/or the RF signal(s) to compensate for a voltage distortion filter created across a modulation bandwidth of the RF signal(s) by coupling the power amplifier circuit with the RF front-end circuit. As a result, it is possible to reduce undesired instantaneous excessive compression and/or spectrum regrowth resulting from the voltage distortion filter to thereby improve efficiency and linearity of the power amplifier circuit(s) across the modulation bandwidth of the RF signal(s).
1. A transmission circuit comprising:
a power amplifier circuit coupled to a transmitter circuit via a radio frequency (RF) front-end circuit and configured to amplify an RF signal based on a modulated voltage and provide the amplified RF signal to the RF front-end circuit;
an envelope tracking (ET) integrated circuit (ETIC) configured to generate the modulated voltage based on a modulated target voltage; and
a transceiver circuit configured to:
generate the RF signal from a time-variant modulation vector;
generate the modulated target voltage as a function of the time-variant modulation vector; and
apply at least one complex filter to at least the RF signal to compensate for a voltage distortion filter created on an output stage of the power amplifier circuit by coupling the power amplifier circuit with the RF front-end circuit across a modulation bandwidth.
2. The transmission circuit of claim 1 , wherein the at least one complex filter comprises an equalization filter and a digital frequency equalization filter and the transceiver circuit is further configured to apply the equalization filter and the digital frequency equalization filter to the time-variant modulation vector.
3. The transmission circuit of claim 2 , wherein the transceiver circuit comprises:
a signal processing circuit configured to generate the RF signal from the time-variant modulation vector;
a target voltage circuit comprising:
an ET lookup table (LUT) circuit configured according to a selected frequency of the RF signal to generate the modulated target voltage; and
an equalizer circuit configured to apply the equalization filter to the time-variant modulation vector to generate a filtered time-variant modulation vector; and
a digital frequency equalizer configured to apply the digital frequency equalization filter to the time-variant modulation vector to generate an equalized time-variant modulation vector.
4. The transmission circuit of claim 3 , wherein the target voltage circuit further comprises a vector-to-real (V2R) converter coupled to the equalizer circuit and configured to extract a selected real parameter from the filtered time-variant modulation vector.
5. The transmission circuit of claim 4 , wherein the target voltage circuit further comprises a scaler coupled to the V2R converter and configured to scale the selected real parameter based on a scaling factor that is adapted according to an average power of the RF signal.
6. The transmission circuit of claim 4 , wherein the target voltage circuit further comprises a unit converter configured to convert the selected real parameter to a predefined parameter configured in the ET LUT circuit for generating the modulated target voltage.
7. The transmission circuit of claim 3 , wherein the equalization filter is expressed as: H EQ (s)=1/H RF (s), wherein:
H EQ (s) represents the equalization filter; and
H RF (s) represents a transfer function of the RF front-end circuit.
8. The transmission circuit of claim 3 , wherein the digital frequency equalization filter is expressed as H F (s)=[1/H EQ (s)]*[1/H RF (s)], wherein:
H F (s) represents the digital frequency equalization filter;
H ET (s) represents a combined complex filter configured to match a combined signal path filter, the combined complex filter is expressed as: H ET (s)=H EQ (s)*H PA (s)*H IV (s), wherein:
H IQ (s) represents a transfer function of the signal processing circuit;
H PA (s) represents a voltage gain transfer function of the power amplifier circuit; and
H IV (s) represents the voltage distortion filter created on the output stage of the power amplifier circuit by coupling the power amplifier circuit with the RF front-end circuit; and
H RF (s) represents a transfer function of the RF front-end circuit.
9. The transmission circuit of claim 3 , wherein the signal processing circuit comprises:
a memory digital predistortion (mDPD) circuit configured to digitally pre-distort the equalized time-variant modulation vector to generate a pre-distorted time-variant modulation vector; and
a modulator circuit configured to generate the RF signal from the pre-distorted time-variant modulation vector and provide the RF signal to the power amplifier circuit.
10. The transmission circuit of claim 2 , wherein the at least one complex filter further comprises an analog frequency equalization filter.
11. The transmission circuit of claim 10 , wherein the transceiver circuit comprises:
a digital frequency equalizer configured to apply the digital frequency equalization filter to the time-variant modulation vector to generate an equalized time-variant modulation vector;
a target voltage circuit comprising:
an ET lookup table (LUT) circuit configured according to a selected frequency of the RF signal to generate the modulated target voltage; and
an equalizer circuit configured to apply the equalization filter to the equalized time-variant modulation vector to generate a filtered time-variant modulation vector;
a signal processing circuit configured to generate the RF signal from the equalized time-variant modulation vector; and
an analog frequency equalizer configured to apply the analog frequency equalization filter to the RF signal.
12. The transmission circuit of claim 11 , wherein the equalization filter is expressed as: H EQ (s)=1, wherein H EQ (s) represents the equalization filter.
13. The transmission circuit of claim 11 , wherein the target voltage circuit further comprises a vector-to-real (V2R) converter coupled to the equalizer circuit and configured to extract a selected real parameter from the filtered time-variant modulation vector.
14. The transmission circuit of claim 13 , wherein the target voltage circuit further comprises a scaler coupled to the V2R converter and configured to scale the selected real parameter based on a scaling factor that is adapted according to an average power of the RF signal.
15. The transmission circuit of claim 13 , wherein the target voltage circuit further comprises a unit converter configured to convert the selected real parameter to a predefined parameter configured in the ET LUT circuit for generating the modulated target voltage.
16. The transmission circuit of claim 11 , wherein:
the digital frequency equalization filter is expressed as H F1 (s)=1/H RF (s), wherein:
H F1 (s) represents the digital frequency equalization filter; and
H RF (s) represents a transfer function of the RF front-end circuit; and
the analog frequency equalization filter is expressed as H F2 (s)=1/H ET (s), wherein:
H F2 (s) represents the analog frequency equalization filter; and
H ET (s) represents a combined complex filter configured to match a combined signal path filter, the combined complex filter is expressed as: H ET (s)=H IQ (s)*H PA (s)*H IV (s), wherein:
H IQ (s) represents a transfer function of the signal processing circuit;
H PA (s) represents a voltage gain transfer function of the power amplifier circuit; and
H IV (s) represents the voltage distortion filter created on the output stage of the power amplifier circuit by coupling the power amplifier circuit with the RF front-end circuit.
17. The transmission circuit of claim 11 , wherein the signal processing circuit comprises:
a memory digital predistortion (mDPD) circuit configured to digitally pre-distort the equalized time-variant modulation vector to generate a pre-distorted time-variant modulation vector; and
a modulator circuit configured to generate the RF signal from the pre-distorted time-variant modulation vector and provide the RF signal to the power amplifier circuit.