Efficient central processing unit overcommit for virtual machines with symmetric multi-processing
Efficient central processing unit overcommit for virtual machines with symmetric multi-processing may be provided by, in response to receiving a preemption-disable request on behalf of a virtual machine (VM) running on a physical central processing unit (PCPU), initiating a counter on the PCPU; in response to receiving a preempting task from a hypervisor to perform on the PCPU, checking a counter status for the counter; in response to the counter status being active: performing an ongoing task from the VM on the PCPU; and delaying performance of the preempting task until the counter status is inactive.
1. A method performed by a computer system, the method comprising:
receiving a preemption-disable request on behalf of a virtual machine (VM) running on a physical central processing unit (PCPU);
determining that the VM is a Simultaneous Multi-Processing (SMP) VM;
in response to receiving the preemption-disable request and determining that the VM is a SMP VM, initiating a counter on the PCPU to a counter value, wherein the counter value is dynamically determined by the computer system based on one or more factors;
in response to receiving a preempting task from a hypervisor to perform on the PCPU, checking a counter status for the counter; and
in response to the counter status being active:
performing an ongoing task from the VM on the PCPU; and
delaying performance of the preempting task until the counter status is inactive.
2. The method of claim 1 , wherein the counter status is set to inactive in response to a timeout condition occurring a predefined amount of time or cycles after the preemption-disable request was received.
3. The method of claim 1 , wherein the counter status is set to inactive in response receiving a preemption-enable request associated with the ongoing task completing a critical-section.
4. The method of claim 1 , further comprising, after the counter status is set to inactive:
in response to receiving a second preempting task from the hypervisor to perform on the PCPU while a second ongoing task is being executed on the PCPU, checking the counter status;
in response to the counter status being inactive:
interrupting the second ongoing task;
performing the second preempting tasks; and
rescheduling the PCPU to resume performing the second ongoing task.
5. The method of claim 1 , wherein the VM includes at least two Virtual Central Processing Units (VCPU) executing on a corresponding at least two PCPUs including the PCPU, wherein each PCPU of the corresponding at least two PCPUs initiate a corresponding counter in response to the preemption-disable request generated by one VCPU of the at least two VCPUs.
6. The method of claim 1 , wherein the hypervisor sets an initial value for the counter and notifies the VM that hypervisor preemption has been temporarily disabled when the counter status is set to active.
7. The method of claim 1 , wherein a guest operating system (OS) of the VM sets an initial value for the counter and sets the counter status to active when a thread enters a critical-section, and wherein the guest OS clears the counter and sets the counter status to inactive when the thread exits the critical-section.
8. The method of claim 7 , wherein the guest OS sets the counter when the guest OS locally disables interrupts.
9. The method of claim 1 , wherein the one or more factors include an operational condition of the computer system, a type or category of the virtual machine, or a level of processor demand at the PCPU.
10. The method of claim 1 , wherein the one or more factors include a type of the ongoing task, a number of PCPUs for which hypervisor preemption is disabled, a number of PCPUs that will be affected by the preemption-disable request, or a current workload associated with the computer system.
11. A system, comprising:
a processor; and
a memory including instructions that when executed by the processor perform operations comprising:
receiving a preemption-disable request on behalf of a virtual machine (VM) running on a physical central processing unit (PCPU);
determining that the VM is a Simultaneous Multi-Processing (SMP) VM;
in response to receiving the preemption-disable request and determining that the VM is a SMP VM, initiating a counter on the PCPU to a counter value, wherein the counter value is dynamically determined by the system based on one or more factors;
in response to receiving a preempting task from a hypervisor to perform on the PCPU, checking a counter status for the counter; and
in response to the counter status being active:
performing an ongoing task from the VM on the PCPU; and
delaying performance of the preempting task until the counter status is inactive.
12. The system of claim 11 , wherein the counter status is set to inactive in response to a timeout condition occurring a predefined amount of time or cycles after the preemption-disable request was received.
13. The system of claim 11 , wherein the counter status is set to inactive in response receiving a preemption-enable request associated with the ongoing task completing a critical-section.
14. The system of claim 11 , wherein the VM includes at least two Virtual Central Processing Units (VCPU) executing on a corresponding at least two PCPUs including the PCPU, wherein each PCPU of the corresponding at least two PCPUs initiate a corresponding counter in response to the preemption-disable request generated by one VCPU of the at least two VCPUs.
15. The system of claim 11 , wherein the hypervisor sets an initial value for the counter and notifies the VM that hypervisor preemption has been temporarily disabled when the counter status is set to active.
16. The system of claim 11 , wherein a guest operating system (OS) of the VM sets an initial value for the counter and sets the counter status to active when a thread enters a critical-section and the guest OS locally disables interrupts, and wherein the guest OS clears the counter and sets the counter status to inactive when the thread exits the critical-section.
17. A memory device that comprises a non-transitory computer-readable medium, the non-transitory computer-readable medium including instructions that when executed by a processor of a system cause the processor to perform operations comprising:
receiving a preemption-disable request on behalf of a virtual machine (VM) running on a physical central processing unit (PCPU);
determining that the VM is a Simultaneous Multi-Processing (SMP) VM;
in response to receiving the preemption-disable request and determining that the VM is a SMP VM, initiating a counter on the PCPU to a counter value, wherein the counter value is dynamically determined by the system based on one or more factors;
in response to receiving a preempting task from a hypervisor to perform on the PCPU, checking a counter status for the counter; and
in response to the counter status being active:
performing an ongoing task from the VM on the PCPU; and
delaying performance of the preempting task until the counter status is inactive.