Memory controller and memory access control method

1. A memory controller that controls access to a Synchronous Dynamic Random Access Memory (SDRAM) including banks, the memory controller comprising:

a receiver that receives a memory access request from an access master;

a selector that selects one of a first issue mode and a second issue mode each related to command issuing;

an issuer that issues a command sequence to the SDRAM in response to the memory access request, in accordance with the one of the first issue mode and the second issue mode which is selected by the selector; and

a determiner that

(i) determines, when the receiver receives the memory access request, whether or not the issuer has a prior unissued command corresponding to a prior memory access request received prior to the memory access request, the prior unissued command not having been issued from the issuer, and

(ii) determines, when the determiner determines that the issuer has the prior unissued command, whether or not a bank corresponding to the memory access request among the banks is different from a bank corresponding to the prior unissued command among the banks, the prior unissued command being a read command or a write command,

wherein

the first issue mode is a mode in which an activation command for activating a bank among the banks is issued in continuous clock cycles without dividing the activation command, the activation command being included in the command sequence,

the second issue mode is a mode in which the activation command is divided and issued in non-continuous clock cycles, and

when the determiner determines that the bank corresponding to the memory access request is different from the bank corresponding to the prior unissued command, the selector performs the selecting.

2. The memory controller according to claim 1 , wherein

when the determiner determines that the issuer does not have the prior unissued command, the selector selects the first issue mode.

3. The memory controller according to claim 1 , wherein

the selector selects the first issue mode when the access master from which the receiver has received the memory access request is a first access master among a plurality of access masters, and

the selector selects the second issue mode when the access master is a second access master among the plurality of access masters.

4. The memory controller according to claim 1 , wherein

the receiver receives a mode designation command designating one of the first issue mode and the second issue mode, and

the selector performs the selecting in accordance with the mode designation command.

5. The memory controller according to claim 1 , further comprising:

a memory holding flag information designating one of the first issue mode and the second issue mode, wherein

the selector reads the flag information from the memory, and performs the selecting in accordance with the flag information read.

6. The memory controller according to claim 5 , wherein

the receiver receives a mode designation command designating one of the first issue mode and the second issue mode, generates the flag information in accordance with the mode designation command, and stores the flag information into the memory.

7. The memory controller according to claim 4 , wherein

the receiver receives the mode designation command from the access master or another device.

8. The memory controller according to claim 5 , wherein

the flag information is stored in the memory for each of a plurality of access masters including the access master, and

the selector reads the flag information corresponding to the access master from which the receiver has received the memory access request, and performs the selecting in accordance with the flag information read.

9. A memory access control method of controlling access to a Synchronous Dynamic Random Access Memory (SDRAM) including banks, the memory access control method comprising:

receiving a memory access request from an access master;

selecting one of a first issue mode and a second issue mode each related to command issuing;

issuing a command sequence to the SDRAM in response to the memory access request in accordance with the one of the first issue mode and the second issue mode which is selected in the selecting;

determining, when the memory access request is received in the receiving, whether or not a prior unissued command corresponding to a prior memory access request received prior to the memory access request is present, the prior unissued command not having been issued; and

determining, when the prior unissued command is determined to be present, whether or not a bank corresponding to the memory access request among the banks is different from a bank corresponding to the prior unissued command among the banks,

wherein

the first issue mode is a mode in which an activation command for activating a bank among the banks is issued in continuous clock cycles without dividing the activation command, the activation command being included in the command sequence,

the second issue mode is a mode in which the activation command is divided and issued in non-continuous clock cycles, and

the selecting is performed when the bank corresponding to the memory access request is determined to be different from the bank corresponding to the prior unissued command.

10. The memory access control method according to claim 9 , wherein

in the selecting, the first issue mode is selected when the prior unissued command is not determined to be present.

11. The memory access control method according to claim 9 , wherein

in the selecting,

the first issue mode is selected when the access master from which the memory access request has been received in the receiving is a first access master among a plurality of access masters, and

the second issue mode is selected when the access master is a second access master among the plurality of access masters.

12. The memory access control method according to claim 9 , further comprising:

receiving a mode designation command designating one of the first issue mode and the second issue mode, wherein

the selecting is performed in accordance with the mode designation command.

13. The memory access control method according to claim 9 , wherein

the selecting includes:

reading, from a memory, flag information designating one of the first issue mode and the second issue mode; and

selecting one of the first issue mode and the second issue mode in accordance with the flag information read in the reading.

14. The memory access control method according to claim 13 , further comprising:

receiving a mode designation command designating one of the first issue mode and the second issue mode;

generating the flag information in accordance with the mode designation command; and

storing the flag information into the memory.

15. The memory access control method according to claim 12 , further comprising:

receiving the mode designation command from the access master or another device.

16. The memory access control method according to claim 13 , wherein

the flag information is stored in the memory for each of a plurality of access masters including the access master, and

the selecting includes:

reading the flag information corresponding to the access master from which the memory access request has been received; and

selecting one of the first issue mode and the second issue mode in accordance with the flag information read in the reading.