Securing conditional speculative instruction execution
View Patent ↗A method performed in a processor, includes: receiving, in the processor, a branch instruction in the processing; determining, by the processor, an address of an instruction after the branch instruction as a candidate for speculative execution, the address including an object identification and an offset; and determining, by the processor, whether or not to perform speculative execution of the instruction after the branch instruction based on the object identification of the address.
1. A device, comprising:
a microprocessor, having:
a register configured to store a memory address having a portion identifying a first object; and
an execution unit configured to execute a branch instruction using the memory address in the register, wherein whether the branch instruction is allowed to be executed in the execution unit is based on the portion identifying the first object.
2. The device of claim 1 , comprising:
a memory configured to store the first object represented by the portion identifying the first object;
wherein the memory address further has a portion identifying an offset of an instruction in the first object.
3. The device of claim 2 , wherein the memory address has 128 bits.
4. The device of claim 2 , wherein the portion identifying the first object has 64 bits.
5. The device of claim 2 , wherein the portion identifying the offset has 64 bits.
6. The device of claim 1 , wherein the memory address identifies a subsequent instruction to be executed in response to execution of the branch instruction.
7. The device of claim 6 , wherein the microprocessor is configured to:
determine whether the first object is a kernel of an operating system; and
in response to a determination that the first object is the kernel of the operating system, prevent execution of the subsequent instruction.
8. The device of claim 7 , wherein the kernel of the operating system is represented by a predetermined number in a memory address.
9. The device of claim 8 , wherein the predetermined number is zero.
10. The device of claim 6 , wherein the microprocessor is configured to:
determine whether the first object is different from a second object associated with the branch instruction; and
in response to a determination that the first object is different from the second object, prevent execution of the subsequent instruction.
11. A method, comprising:
storing, in a memory, a first object;
storing, by a microprocessor, into a register a memory address having a portion identifying the first object;
executing, by an execution unit of the microprocessor, a branch instruction using the memory address in the register; and
determining, by the microprocessor, whether the branch instruction is allowed to be executed in the execution unit based on the portion identifying the first object.
12. The method of claim 11 , wherein the memory address further has a portion identifying an offset of an instruction in the first object.
13. The method of claim 12 , wherein the portion identifying the first object has 64 bits.
14. The method of claim 12 , wherein the portion identifying the offset has 64 bits.
15. The method of claim 11 , wherein the memory address identifies a subsequent instruction to be executed in response to execution of the branch instruction.
16. The method of claim 15 , further comprising:
determining whether the first object is a kernel of an operating system; and
preventing, in response to a determination that the first object is the kernel of the operating system, execution of the subsequent instruction.
17. The method of claim 15 , further comprising:
determining whether the first object is different from a second object associated with the branch instruction; and
preventing, in response to a determination that the first object is different from the second object, execution of the subsequent instruction.
18. A microprocessor, comprising:
a register configured to store a memory address;
an execution unit configured to execute a branch instruction configured to use the memory address in the register;
wherein the memory address has a first portion and a second portion, the first portion configured to identify an object, the second portion configured to identify an offset of a subsequent instruction stored in the object for execution as a result of executing the branch instruction; and
wherein the microprocessor is configured to determine, based on the first portion, whether to allow execution of the subsequent instruction as the result of executing the branch instruction.
19. The microprocessor of claim 18 , wherein the microprocessor is configured to prevent execution of the subsequent instruction in response to a determination that the object is a kernel of an operating system.
20. The microprocessor of claim 18 , wherein the microprocessor is configured to prevent execution of the subsequent instruction in response to a determination that the object is different from an object associated with the branch instruction.