Method and system for control of sidewall orientation in vertical gallium nitride field effect transistors
A III-N-based vertical transistor includes a III-N substrate, a source, a drain, and a channel comprising a III-N crystal material and extending between the source and the drain. The channel includes at least one sidewall surface aligned ±0.3° with respect to an m-plane of the III-N crystal material. The III-N-based vertical transistor also includes a gate electrically coupled to the at least one sidewall surface of the channel.
1. A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising:
providing the III-nitride substrate;
aligning a mask with respect to the III-nitride substrate;
forming a mask layer including a plurality of mask patterns;
providing a plurality of gate interface regions aligned parallel to one of the < 1 2 1 0> directions of the III-nitride substrate ±0.3° and adjoining a channel region extending between a source region and a drain region;
forming a plurality of gate regions in contact with the plurality of gate interface regions;
forming a gate electrode coupled to the plurality of gate regions;
forming a source electrode coupled to the source region; and
forming a drain electrode coupled to the drain region.
2. The method of claim 1 wherein aligning the mask with respect to the III-nitride substrate comprises:
determining an orientation of an alignment reference structure of the III-nitride substrate, wherein the alignment reference structure defines a reference direction on the III-nitride substrate; and
determining the < 1 2 1 0> directions of the III-nitride substrate.
3. The method of claim 2 further comprising:
computing a difference between the reference direction and the < 1 2 1 0> directions; and
aligning a feature of one or more of the plurality of mask patterns based on the difference.
4. The method of claim 2 further comprising:
computing a difference between the reference direction and the < 1 2 1 0> directions;
aligning the mask to the alignment reference structure; and
thereafter, re-aligning the mask based on the difference.
5. The method of claim 2 wherein determining the < 1 2 1 0> directions of the III-nitride substrate comprises analyzing the III-nitride substrate using at least one of an x-ray diffraction technique or an optical diffraction technique.
6. The method of claim 1 wherein each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the < 1 2 1 0> directions of the III-nitride substrate ±0.3°.
7. The method of claim 1 wherein forming the drain electrode comprises forming a back-side metal electrode on the III-nitride substrate.
8. The method of claim 1 , wherein:
forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.
9. A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising:
providing the III-nitride substrate comprising an alignment reference structure, wherein the alignment reference structure defines a reference direction on the III-nitride substrate;
determining < 1 2 1 0> directions of the III-nitride substrate;
computing a difference between the reference direction and the < 1 2 1 0> directions to define a correction factor;
aligning a mask with respect to the III-nitride substrate using correction factor;
forming a mask layer including a plurality of mask patterns;
providing a plurality of gate interface regions aligned parallel to one of the < 1 2 1 0> directions of the III-nitride substrate ±0.3° and defining a channel region extending between a source region and a drain region;
forming a plurality of gate regions in contact with the plurality of gate interface regions;
forming a gate electrode coupled to the plurality of gate regions;
forming a source electrode coupled to the source region; and
forming a drain electrode coupled to the drain region.
10. The method of claim 9 wherein:
each mask pattern of the plurality of mask patterns includes a feature aligned parallel to one of the < 1 2 1 0> directions of the III-nitride substrate ±0.3°.
11. The method of claim 9 , wherein:
forming the plurality of gate regions comprises epitaxially regrowing the plurality of gate regions.
12. The method of claim 9 , wherein:
providing the plurality of gate interface regions comprises providing a fin defining the channel region vertically extending between the source region and the drain region.
13. The method of claim 9 , wherein aligning the mask comprises:
aligning the mask to the alignment reference structure; and
thereafter, re-aligning the mask based on the correction factor.
14. The method of claim 9 , wherein:
providing the III-nitride substrate comprises providing the alignment reference structure comprising an orientation flat.