IP Library Granted Patent US 11,775,181
Granted Patent B2
US 11,775,181 · App. 17/708,735 · Granted Oct 3, 2023

Read error recovery

Inventors: Xiangang Luo (Fremont, CA); Harish Reddy Singidi (Fremont, CA); Ting Luo (Santa Clara, CA); Kishore Kumar Muchherla (Fremont, CA)
Assignee: Micron Technology, Inc.
G06F3/0619G06F3/0653G06F3/0679
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Quick Facts
Patent No.
US 11,775,181
App. No.
17/708,735
Granted
Oct 3, 2023
Kind
B2
Abstract

Systems and methods are disclosed, including maintaining an error recovery data structure for a set of codewords (CWs) in a storage system, the error recovery data structure storing indications that specific CWs are correctable or not correctable by specific error handing (EH) steps of a set of multiple EH steps, and determine an order of EH steps for the storage system based on the error recovery data structure. Maintaining the error recovery data structure can include determining if each CW of the set of CWs is correctable by a specific EH step, storing indications of CWs determined correctable by the specific EH step in the error recovery data structure, and, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

Claims (72)

1. A system comprising:

a storage system comprising control circuitry and a memory array having multiple groups of memory cells,

wherein the control circuitry is configured to:

maintain an error recovery data structure in the storage system for a set of codewords (CWs), the error recovery data structure storing indications that specific CWs are correctable or not correctable by specific error handing (EH) steps of a set of multiple EH steps; and

determine an order of EH steps for the storage system based on the error recovery data structure.

2. The system of claim 1 ,

wherein, to maintain the error recovery data structure, the control circuitry is configured to:

determine whether each CW of the set of CWs is correctable by a specific EH step;

store an indication of whether the first CW is determined correctable by the specific EH step in the error recovery data structure;

determine if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure; and

in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, increment the specific EH step.

3. The system of claim 2 ,

wherein the control circuitry is configured to:

determine if each CW of the set of CWs is correctable by the incremented EH step; and

in response to determining that each CW of the set of CWs is correctable by the incremented EH step, update the order of EH steps for subsequent error recovery using the incremented EH step.

4. The system of claim 2 ,

wherein, to increment the specific EH step, the control circuitry is configured to:

determine if each CW of the set of CWs is correctable by the incremented EH step;

store indications of the CWs determined correctable by the incremented EH step in the error recovery data structure;

determine if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure; and

in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, increment the incremented EH step.

5. The system of claim 2 ,

wherein, to maintain the error recovery data structure, the control circuitry is configured to perform error recovery for the set of CWs using a first EH step from the set of EH steps,

wherein, to determine if each CW of the set of CWs is correctable by the EH step, the control circuitry is configured to determine if each CW of the set of CWs is correctable by the first EH step,

wherein, to store the indications of the CWs determined correctable by the EH step in the error recovery data structure, the control circuitry is configured to store indications of the CWs determined correctable by the first EH step in the error recovery data structure, and

wherein, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, the control circuitry is configured to increment the first EH step to a second EH step.

6. The system of claim 1 ,

wherein, to maintain the error recovery data structure, the control circuitry is configured to initialize the error recovery data structure having an entry for each CW of the set of CWs to an initial value, and

wherein, to store indications of the CWs determined correctable by the specific EH step, the control circuitry is configured to update values for each CW of the set of CWs in the error recovery data structure.

7. The system of claim 1 ,

wherein to determine the order of EH steps, the control circuitry is configured to determine a minimum subset of the set of EH steps to correct the set of CWs using the error recovery data structure.

8. The system of claim 1 ,

wherein to determine the order of EH steps, the control circuitry is configured to reorder the order of EH steps based on the error recovery data structure.

9. The system of claim 1 ,

wherein the error recovery data structure includes a bitmap having a single value for each of the set of CWs.

10. A method comprising:

maintaining, using control circuitry of a storage system, an error recovery data structure in the storage system for a set of codewords (CWs) associated with one or more memory operations of the storage system, the error recovery data structure storing indications that specific CWs are correctable or not correctable by specific error handing (EH) steps of a set of multiple EH steps; and

determining an order of EH steps for the storage system based on the error recovery data structure.

11. The method of claim 10 ,

wherein maintaining the error recovery data structure comprises:

determining whether each CW of the set of CWs is correctable by a specific EH step;

storing an indication of whether the first CW is determined correctable by the specific EH step in the error recovery data structure;

determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure; and

in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the specific EH step.

12. The method of claim 11 ,

wherein maintaining the error recovery data structure comprises determining if each CW of the set of CWs is correctable by the incremented EH step, and

wherein determining the order of EH steps for the storage system comprises, in response to determining that each CW of the set of CWs is correctable by the incremented EH step, updating the order of EH steps for subsequent error recovery using the incremented EH step.

13. The method of claim 11 ,

wherein incrementing the specific EH step comprises:

determining if each CW of the set of CWs is correctable by the incremented EH step;

storing indications of the CWs determined correctable by the incremented EH step in the error recovery data structure;

determining if one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure; and

in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the incremented EH step.

14. The method of claim 11 ,

wherein maintaining the error recovery data structure comprises performing error recovery for the set of CWs using a first EH step from the set of EH steps,

wherein determining if each CW of the set of CWs is correctable by the EH step comprises determining if each CW of the set of CWs is correctable by the first EH step,

wherein storing the indications of the CWs determined correctable by the EH step in the error recovery data structure comprises storing indications of the CWs determined correctable by the first EH step in the error recovery data structure, and

wherein incrementing the specific EH step comprises, in response to determining that one or more CW in the set of CWs are not indicated as correctable in the error recovery data structure, incrementing the first EH step to a second EH step.

15. The method of claim 10 ,

wherein maintaining the error recovery data structure comprises initializing the error recovery data structure having an entry for each CW of the set of CWs to an initial value, and

wherein storing indications of the CWs determined correctable by the specific EH step comprises updating values for each CW of the set of CWs in the error recovery data structure.

16. The method of claim 10 ,

wherein determining the order of EH steps comprises determining a minimum subset of the set of EH steps to correct the set of CWs using the error recovery data structure.

17. The method of claim 10 ,

wherein determining the order of EH steps comprises reordering the order of EH steps based on the error recovery data structure.

18. The method of claim 10 ,

wherein the error recovery data structure includes a bitmap having a single value for each of the set of CWs.

19. A non-transitory device-readable storage medium comprising instructions that, when executed by controller circuitry of a storage system, cause the storage system to perform operations comprising:

maintaining an error recovery data structure in the storage system for a set of codewords (CWs) associated with one or more memory operations of the storage system, the error recovery data structure storing indications that specific CWs are correctable or not correctable by specific error handing (EH) steps of a set of multiple EH steps; and

determining an order of EH steps for the storage system based on the error recovery data structure.

20. The non-transitory device-readable storage medium of claim 19 ,

wherein determining the order of EH steps comprises determining a minimum subset of the set of EH steps to correct the set of CWs using the error recovery data structure.

Continuity (3)
Continuation 17051961
Provisional Application 62668768 · May 8, 2018
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