SOFTWARE-BASED ENTROPY SOURCE BASED ON DRAM ACCESS LATENCIES
In one set of embodiments, a computer system can initiate a memory stress test on a memory subsystem of the computer system, where the memory subsystem including a dynamic random access memory (DRAM). Then, while the memory stress test is running, the computer system can execute a plurality of access operations for accessing the DRAM, measure the time taken to complete each access operation, combine the measured times to compute a value, and output the value as an entropy sample.
1 . A method comprising:
initiating, by a computer system, a memory stress test on a memory subsystem of the computer system, the memory subsystem including a dynamic random access memory (DRAM); and
while the memory stress test is running:
executing, by the computer system, a plurality of access operations for accessing the DRAM;
measuring, by the computer system, a time taken to complete each access operation;
combining, by the computer system, the measured times to compute a value; and
outputting the value.
2 . The method of claim 1 wherein the memory stress test causes high memory bandwidth usage in the memory subsystem that in turn increases variability of DRAM access times.
3 . The method of claim 1 wherein the measuring comprises measuring a number of central processing unit (CPU) clock cycles needed to complete said each access operation.
4 . The method of claim 1 wherein the combining comprises:
extracting a least or most significant bit of eight measured times; and
using the extracted bits to create a random byte value.
5 . The method of claim 1 wherein the combining comprises computing an exclusive OR of bitstring representations of the measured times.
6 . The method of claim 1 wherein the value is an entropy sample that is provided to a random number generator for generating one or more random numbers.
7 . The method of claim 6 wherein the random number generator uses the entropy sample as a seed value for initializing a pseudorandom number generator.
8 . A non-transitory computer readable storage medium having stored thereon program code executable by a computer system, the program code embodying a method comprising:
initiating a memory stress test on a memory subsystem of the computer system, the memory subsystem including a dynamic random access memory (DRAM); and
while the memory stress test is running:
executing a plurality of access operations for accessing the DRAM;
measuring a time taken to complete each access operation;
combining the measured times to compute a value; and
outputting the value.
9 . The non-transitory computer readable storage medium of claim 8 wherein the memory stress test causes high memory bandwidth usage in the memory subsystem that in turn increases variability of DRAM access times.
10 . The non-transitory computer readable storage medium of claim 8 wherein the measuring comprises measuring a number of central processing unit (CPU) clock cycles needed to complete said each access operation.
11 . The non-transitory computer readable storage medium of claim 8 wherein the combining comprises:
extracting a least or most significant bit of eight measured times; and
using the extracted bits to create a random byte value.
12 . The non-transitory computer readable storage medium of claim 8 wherein the combining comprises computing an exclusive OR of bitstring representations of the measured times.
13 . The non-transitory computer readable storage medium of claim 8 wherein the value is an entropy sample that is provided to a random number generator for generating one or more random numbers.
14 . The non-transitory computer readable storage medium of claim 13 wherein the random number generator uses the entropy sample as a seed value for initializing a pseudorandom number generator.
15 . A computer system comprising:
a processor;
a memory subsystem including a dynamic random access memory (DRAM); and
a non-transitory computer readable medium having stored thereon program code that, when executed, causes the processor to:
initiate a memory stress test on the memory subsystem; and
while the memory stress test is running:
execute a plurality of access operations for accessing the DRAM;
measure a time taken to complete each access operation;
combine the measured times to compute a value; and
output the value.
16 . The computer system of claim 15 wherein the memory stress test causes high memory bandwidth usage in the memory subsystem that in turn increases variability of DRAM access times.
17 . The computer system of claim 15 wherein the program code that causes the processor to measure the time needed to complete each access operation comprises program code that causes the processor to measure a number of central processing unit (CPU) clock cycles needed to complete said each access operation.
18 . The computer system of claim 15 wherein the program code that causes the processor to combine the measured times comprises program code that causes the processor to:
extract a least or most significant bit of eight measured times; and
use the extracted bits to create a random byte value.
19 . The computer system of claim 15 wherein the program code that causes the processor to combine the measured times comprises program code that causes the processor to compute an exclusive OR of bitstring representations of the measured times.
20 . The computer system of claim 15 wherein the value is an entropy sample that is provided to a random number generator for generating one or more random numbers.
21 . The computer system of claim 20 wherein the random number generator uses the entropy sample as a seed value for initializing a pseudorandom number generator.