User process identifier based address translation
A processing device of a memory sub-system can receive a first address from a host and can provide the first address to a memory management unit (MMU) for translation. The processing device can also receive a second address from the MMU wherein the second address is translated from the first address. The processing device can further access the memory device utilizing the second address.
1. A system comprising:
a processing device of a host, coupled with a memory device of a memory sub-system, to:
receive a first address from the memory sub-system for translation;
map the first address to a second address utilizing host memory; and
provide the second address to the memory sub-system to access the memory device utilizing the second address.
2. The system of claim 1 , wherein the processing device is configured to receive the first address from a PCIe DMA of the memory sub-system.
3. The system of claim 1 , wherein the processing device is configured to receive the first address via a non-control interface.
4. The system of claim 1 , wherein the processing device is configured to receive the first address via a PCIe interface.
5. The system of claim 1 , wherein the processing device is configured to map the first address to the second address is further configured to map the first address which comprises a virtual address to the second address which comprises a physical address.
6. The system of claim 1 , wherein the processing device is further configured to map the first address to the second address utilizing an identification (ID) incorporated in the first address.
7. The system of claim 6 , wherein the ID corresponds to a user process.
8. The system of claim 6 , wherein the ID corresponds to the memory sub-system.
9. The system of claim 2 , wherein the virtual computing instance is a virtual machine (VM) executed on the host.
10. The system of claim 2 , wherein the virtual computing instance is a container executed on the host.
11. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive a request, at a memory management unit (MMU) of a host, for a process address space identifier (PASID) corresponding to a process of the host;
generate the PASID, wherein the PASID is generated by the MMU;
store the PASID in host memory responsive to generating the PASID; and
provide from the MMU and to a guest operating system (OS) the PASID responsive to receipt of the request.
12. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions are further executable by the processing device to cause the processing device to receive the request from a driver.
13. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions are further executable by the processing device to cause the processing device to receive the request from the host without the request having been modified by the host.
14. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions are further executable by the processing device to cause the processing device to receive the request from a hypervisor without the request having been modified by the hypervisor.
15. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions are further executable by the processing device to cause the processing device to register the PASID with a PASID table of a memory device.
16. The non-transitory computer-readable storage medium of claim 11 , wherein the instructions are further executable by the processing device to cause the processing device to store the PASID in memory pages of the host memory.
17. A method comprising:
generating a process address space identifier (PASID) corresponding to a virtual computing instance;
receiving a request to map a first address, wherein the request is received at a memory management unit (MMU) of a host and from a memory sub-system external to the host;
mapping the first address to a second address utilizing the PASID; and
providing from the MMU and to the memory sub-system the second address.
18. The method of claim 17 , further comprising receiving a different request, at a processing resource of the host, to generate the PASID.
19. The method of claim 18 , further comprising providing the request from the processing resource of the host to the MMU of the host.
20. The method of claim 19 , wherein the MMU generates the PASID.