Reduced data representation memory controller and related chiplet sets
A transform memory controller is described herein wherein the transform memory controller comprises logic elements configured to perform desired transform operations on data that flows to-and-from conventional computer memory elements. The transform operations are configured to perform operations on such data without the need for such data to travel to-and-from the conventional computer memory element via the processor (e.g., Central Processing Unit (CPU)) of the computer system. Several desirable transform operations are herein disclosed.
1. A transform memory controller, the controller being a part of a computer system further comprising a processor and a hierarchy of computer memory elements which are all accessed by the processor using read by address or content or write by address or content, the transform memory controller comprising:
an input, the input receiving data signals from at least one of the computer memory elements which is accessed by the transform memory controller using read by address or content separate from access of the computer memory element by the processor;
a set of logic elements, the set of logic elements configured to perform a at least one transform operation on the data signals received by the input, wherein the transform operation performs a desired computation on the data signals without the desired computation being performed by the processor of the computer system; and
an output, the output of the transform operation sends results of the desired computation to at least one of the computer memory elements which is accessed by the transform memory controller using write by address or content separate from access of the computer memory element by the processor.
2. The transform memory controller of claim 1 wherein:
the set of logic elements comprise a chiplet, said chiplet configured to be in electronic communications with neighboring computer memory elements in the hierarchy.
3. The transform memory controller of claim 2 wherein:
the chiplet is mechanically mated to a substrate, the substrate comprising the neighboring computer memory elements mechanically mated to the substrate.
4. The transform memory controller of claim 3 wherein the chiplet is in electronic communications with the neighboring computer memory elements via an interconnect fabric.
5. The transform memory controller of claim 3 wherein the substrate further comprises a communication bus, the bus providing communications between the chiplet and the neighboring computer memory elements.
6. The transform memory controller of claim 3 wherein the neighboring computer memory elements further comprises DRAM elements.
7. The transform memory controller of claim 1 wherein said set of logic elements are constructed integrally with the processor to comprise a System On a Chip (SOC).
8. The transform memory controller of claim 1 wherein the processor of the computer system is one of a group, the group comprising of at least one of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU).
9. The transform memory controller of claim 8 wherein the transform operation to be performed on the data signals comprises a computation on data of a desired size at the transform memory controller instead of the data signals being transferred to the processor of the computer system.
10. The transform memory controller of claim 9 wherein the computer system is configured to have the transform memory controller perform a transform operation on data signals that have a desired threshold of energy cost, if performed by the processor of the computer system.
11. The transform memory controller of claim 9 wherein the computer system is configured to have the transform memory controller perform a transform operation on data signals that have a desired threshold of time delay, if performed by the processor of the computer system.
12. The transform memory controller of claim 1 wherein one of the transform operations comprises a random linear algebra (RandNLA) operation.
13. The transform memory controller of claim 12 wherein the RandNLA operation comprises a sketching matrix that performs a projection of a linear algebra problem to a lower dimensional subspace.
14. The transform memory controller of claim 12 wherein the RandNLA operation comprises performing a least-square computation in a sketched subspace.
15. The transform memory controller of claim 1 wherein one of the transform operations comprises subsampling operations on a data matrix.
16. The transform memory controller of claim 15 wherein the subsampling operation on a data matrix comprises a search of a data list, the subsampling operation employing reduced size thumbnails of the data matrix.
17. A transform memory controller being a part of a computer system further comprising a processor and a hierarchy of computer memory elements, the transform memory controller comprising:
an input of a transform chiplet operatively coupled to at least one computer memory element in a hierarchy of computer memory elements including main memory which are all accessed by the processor using at least one of read by address, read by content, write by address, write by content, or any combination, the at least one computer memory element being accessed by the transform memory controller using read by address or content under control of memory address and address decoder and separate from the processor;
a set of logic elements in the transform chiplet coupled to transform storage memory via a high bandwidth chip interconnect fabric, the transform storage memory comprising at least one computer memory element in the hierarchy, the set of logic elements configured to perform a transform operation on data signals received by the input wherein the transform operation performs a desired computation on the data signals storing results in the transform storage memory without the desired computation being performed by the processor of the computer system; and
an output of the transform chiplet operatively coupled to at least one computer memory element in the hierarchy, thereby sending results of the transform operation to the at least one computer memory element in the hierarchy which is accessed by the transform memory controller using write by address or content under control of memory address and address decoder and separate from the processor.
18. A transform memory controller in a computer system, comprising:
an input of a transform chiplet, the input receiving data signals from at least one computer memory element in a hierarchy of computer memory elements including main memory which are all accessed by a processor, comprising at least one of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), or both, of the computer system using at least one of read by address, read by content, write by address, write by content, or any combination, at least one computer memory element in the hierarchy being accessed by the transform memory controller using read by address or content separate from access of the computer memory element by the processor;
a set of logic elements operatively coupled to a transform storage memory comprising at least one computer memory element in the hierarchy, the transform storage memory includes at least one DRAM element mechanically and/or electronically coupled to the transform chiplet via short communication pathways based on a high bandwidth chip interconnect that reduces delay in transferring data signals between the transform storage memory and the transform memory controller, the set of logic elements configured to perform a transform operation including a RandNLA operation that comprises a sketching matrix, on the data signals received by the input wherein the transform operation performs a projection of a linear algebra problem to a lower dimensional subspace on the data signals while storing, at least in part, results of the transform operation in the transform storage memory, without the transform operation being performed by the processor; and
an output of the transform chiplet, the output sends the results of the transform operation from the transform chiplet, via short communication pathways based on a high bandwidth chip interconnect that reduces delay in transferring the results, to the main memory which is accessed by the transform memory controller using write by address or content separate from access of the main memory by the processor.