Configurable cache for multi-endpoint heterogeneous coherent system

1. A circuit comprising:

a cache configuration register; and

a controller coupled to the cache configuration register, the controller configured to:

receive a random allocation pointer;

retrieve an AND mask from the cache configuration register;

retrieve an OR mask from the cache configuration register;

perform a first AND operation with a first bit of the random allocation pointer and a first AND mask bit to generate a first output bit;

perform a second AND operation with a second bit of the random allocation pointer and a second AND mask bit to generate a second output bit;

perform a first OR operation with the first output bit and a first OR mask bit to generate a first way identifier bit; and

perform a second OR operation with the second output bit and a second OR mask bit to generate a second way identifier bit.

2. The circuit of claim 1 , wherein:

a set of most significant bits of the random allocation pointer is a way group identifier.

3. The circuit of claim 2 , wherein:

the set of most significant bits of the random allocation pointer includes three most significant bits.

4. The circuit of claim 2 , wherein:

the controller is configured to allocate a way to one of an addressable memory space and a data cache; and

the way is allocated based on the first way identifier bit, the second way identifier bit, and the way group identifier.

5. The circuit of claim 1 , wherein:

the controller is configured to receive a memory access request from a requesting device; and

the controller retrieves the AND mask and the OR mask based on a characteristic of the requesting device.

6. The circuit of claim 5 , wherein:

the characteristic is one of real-time or non-real-time.

7. The circuit of claim 5 , wherein:

the way is allocated to a cache tag associated with the memory access request based on the first way identifier bit, the second way identifier bit, and a way group identifier.

8. A method comprising:

receive, by a controller, a random allocation pointer;

retrieving, by the controller, an AND mask from a cache configuration register coupled to the controller;

retrieving, by the controller, an OR mask from the cache configuration register;

performing, by the controller, a first AND operation with a first bit of the random allocation pointer and a first AND mask bit to generate a first output bit;

performing, by the controller, a second AND operation with a second bit of the random allocation pointer and a second AND mask bit to generate a second output bit;

performing, by the controller, a first OR operation with the first output bit and a first OR mask bit to generate a first way identifier bit; and

performing, by the controller, a second OR operation with the second output bit and a second OR mask bit to generate a second way identifier bit.

9. The method of claim 8 , wherein:

a set of most significant bits of the random allocation pointer is a way group identifier.

10. The method of claim 9 , wherein:

the set of most significant bits of the random allocation pointer includes three most significant bits.

11. The method of claim 9 , further comprising:

allocating, by the controller, a way to one of an addressable memory space and a data cache; wherein the way is allocated based on the first way identifier bit, the second way identifier bit, and the way group identifier.

12. The method of claim 8 , further comprising:

receiving, by the controller, a memory access request from a requesting device;

wherein the controller retrieves the AND mask and the OR mask based on a characteristic of the requesting device.

13. The method of claim 12 , wherein:

the characteristic is one of real-time or non-real-time.

14. The method of claim 12 , further comprising:

allocating, by the controller, the way to a cache tag associated with the memory access request based on the first way identifier bit, the second way identifier bit, and a way group identifier.

15. A system comprising:

a memory;

a cache configuration register; and

a controller coupled to the cache configuration register and the memory, the controller configured to:

receive a random allocation pointer;

retrieve an AND mask from the cache configuration register;

retrieve an OR mask from the cache configuration register;

perform a first AND operation with a first bit of the random allocation pointer and a first AND mask bit to generate a first output bit;

perform a second AND operation with a second bit of the random allocation pointer and a second AND mask bit to generate a second output bit;

perform a first OR operation with the first output bit and a first OR mask bit to generate a first way identifier bit; and

perform a second OR operation with the second output bit and a second OR mask bit to generate a second way identifier bit.

16. The system of claim 15 , wherein:

a set of most significant bits of the random allocation pointer is a way group identifier.

17. The system of claim 16 , wherein:

the set of most significant bits of the random allocation pointer includes three most significant bits.

18. The system of claim 16 , wherein:

the controller is configured to allocate a way to one of an addressable memory space and a data cache; and

the way is allocated based on the first way identifier bit, the second way identifier bit, and the way group identifier.

19. The system of claim 15 , wherein:

the controller is configured to receive a memory access request from a requesting device; and

the controller retrieves the AND mask and the OR mask based on a characteristic of the requesting device.

20. The system of claim 19 , wherein:

the way is allocated to a cache tag associated with the memory access request based on the first way identifier bit, the second way identifier bit, and a way group identifier.