Parasitic pulse cancelation circuit

1. A motor control system comprising:

a direct current (DC) motor including a rotor induced to rotate in response to a drive current generated by a supply voltage, the rotation of the rotor generating a mechanical force that drives a component;

a ripple count circuit including an active filter circuit and a parasitic pulse cancellation circuit,

wherein the active filter circuit is configured to filter the drive current and to generate a pulsed signal containing at least one parasitic pulse; and

wherein the parasitic pulse cancelation circuit is in signal communication with the ripple count circuit to receive the pulsed signal and to output a ripple count signal based on the pulsed signal, the ripple count signal excluding the at least one parasitic pulse,

wherein the parasitic pulse cancelation circuit includes a pulse cancellation filter configured to receive the pulsed signal from the active filter circuit and to output a filtered pulsed signal based on the pulsed signal, and

wherein the parasitic pulse cancelation circuit includes a logic gate having a first input configured to receive pulsed signal from the active filter circuit and a second input configured to receive the filtered pulsed signal from the pulse cancellation filter, the logic gate configured to generate the ripple count signal based on a first voltage level corresponding to the pulsed signal applied to the first input and a second voltage level corresponding to the filtered pulsed signal applied to the second input,

wherein the ripple count signal has a logic high state in response to both the first voltage level and the second voltage level exceed a reference voltage and has a logic low state in response in response to both the first voltage level and the second voltage level being below the reference voltage.

2. The motor control system of claim 1 , wherein the logic gate is an OR gate.

3. The motor control system of claim 1 , wherein the pulsed signal has a time period (T) and the at least one parasitic pulse occurs during a targeted time duration (t0) of the period (T), and

wherein the ripple count signal defines a time period (T) excluding the at least one parasitic pulse during the targeted time duration (t0).

4. The motor control system of claim 1 , wherein the logic gate has a voltage threshold, the logic gate configured to determine a first logic state of the first and second inputs and in response to a voltage applied thereto being greater than or equal to the voltage threshold, and to determine a second logic state of the first and second inputs and in response to a voltage applied thereto being less than the voltage threshold.

5. The motor control system of claim 1 , wherein the parasitic pulse cancelation circuit outputs the ripple count signal in response to maintaining the second voltage of the filtered pulsed signal above the voltage threshold while a voltage of the at least one parasitic pulse is below the voltage threshold.

6. A method of controlling a motor control system, the method comprising:

generating a drive current using a supply voltage and delivering the drive current to a direct current (DC) motor;

rotating a rotor of the motor in response to the drive current to drive a component;

filtering the drive current using an active filter circuit and generating a pulsed signal based on the filtered drive current, the pulsed signal containing at least one parasitic pulse; and

delivering the pulsed signal to the parasitic pulse cancelation circuit and generating, via the parasitic pulse cancelation circuit, a ripple count signal based on the pulsed signal, the ripple count signal excluding the at least one parasitic pulse,

wherein generating the ripple count signal includes:

delivering the pulsed signal to a pulse cancellation filter included in the parasitic pulse cancelation circuit, and filtering, via the parasitic pulse cancelation circuit, the pulsed signal to generate a filtered pulsed signal;

outputting the pulsed signal from the active filter circuit to the logic gate to apply a first voltage level to a first input of a logic gate included in the parasitic pulse cancelation circuit;

outputting the filtered pulsed signal from the pulse cancellation filter to the logic gate to apply a second voltage level to a second input of the logic gate; and

outputting the ripple count signal from the logic gate based on the first voltage level corresponding to the pulsed signal and the second voltage level corresponding to the filtered pulsed signal,

wherein the ripple count signal has a logic high state in response to both the first voltage level and the second voltage level exceed a reference voltage and has a logic low state in response in response to both the first voltage level and the second voltage level being below the reference voltage.

7. The method of claim 6 , wherein the logic gate is an OR gate and the ripple count signal is generated according to digital logic of the OR gate.

8. The method of claim 6 , wherein the pulsed signal has a time period (T) and the at least one parasitic pulse occurs during a targeted time duration (t0) of the period (T), and

wherein the ripple count signal defines a time period (T) excluding the at least one parasitic pulse during the targeted time duration (t0).

9. The method of claim 6 , further comprising:

determining, via the logic gate, a first logic state of the first and second inputs in response to a voltage applied thereto being greater than or equal to a voltage threshold;

determining a second logic state of the first and second inputs in response to a voltage applied thereto being less than the voltage threshold, and

outputting, via the parasitic pulse cancelation circuit, the ripple count signal in response to maintaining the second voltage of the filtered pulsed signal above the voltage threshold while a voltage of the at least one parasitic pulse is below the voltage threshold.