Memory array having air gaps

1. A method, comprising:

forming a memory array comprising:

forming chalcogenide memory cells;

forming a dielectric material that separates a plurality of first word lines from one another and a plurality of second word lines from one another; and

forming a sealing material on sidewalls of the dielectric material;

removing, via a plurality of cavities, at least a portion of the sealing material to expose the dielectric material; and

forming, based at least in part on exposing the dielectric material, one or more voids in the dielectric material, the one or more voids separating the plurality of first word lines from one another and the plurality of second word lines from one another.

2. The method of claim 1 , wherein forming the one or more voids comprises:

removing at least a portion of the dielectric material to form the one or more voids between a plurality of chalcogenide memory cells of the memory array.

3. The method of claim 2 , wherein a second portion of the dielectric material remains on sidewalls of the plurality of chalcogenide memory cells based at least in part on removing the portion of the dielectric material.

4. The method of claim 1 , further comprising:

depositing, based at least in part on forming the one or more voids, an insulating material on sidewalls at least partially surrounding the one or more voids.

5. The method of claim 1 , further comprising:

forming, via the plurality of cavities and based at least in part on forming the one or more voids, a cap on openings to the one or more voids to the plurality of cavities.

6. The method of claim 1 , further comprising:

forming, based at least in part on forming the one or more voids, a plurality of piers in the plurality of cavities, wherein the one or more voids are at least partially enclosed based at least in part on forming the plurality of piers.

7. The method of claim 6 , wherein:

a pillar of a plurality of pillars comprises a conductive material and is for accessing a chalcogenide memory cell of a plurality of chalcogenide memory cells of the memory array, and

a pier of the plurality of piers comprises a second dielectric material and is for supporting the memory array.

8. The method of claim 1 , wherein the one or more voids comprise atmospheric air, a gas, or a combination of gases.

9. The method of claim 1 , wherein, prior to removing the portion of the sealing material:

the plurality of first word lines are separated from one another and the plurality of second word lines are separated from one another by the dielectric material in a first direction,

the plurality of cavities and the sealing material extend in the first direction, and

the dielectric material is separated from an interior of the plurality of cavities by the sealing material in a second direction that is orthogonal to the first direction and a third direction that is orthogonal to the first direction.

10. The method of claim 1 , wherein the memory array is a three-dimensional memory array.

11. An apparatus, comprising:

a memory array comprising:

a plurality of memory cells comprising a chalcogenide material;

a plurality of first word lines;

a plurality of second word lines;

a plurality of pillars; and

a plurality of piers, wherein:

the plurality of first word lines are separated from one another by one or more first voids, and

the plurality of second word lines are separated from one another by one or more second voids.

12. The apparatus of claim 11 , wherein:

first sidewalls at least partially surrounding the one or more first voids comprise an insulating material separating an interior of the one or more first voids from an exterior of adjacent memory cells of the plurality of memory cells, and

second sidewalls at least partially surrounding the one or more second voids comprise the insulating material separating an interior of the one or more second voids from an exterior of adjacent second memory cells of the plurality of memory cells.

13. The apparatus of claim 11 , wherein a capacitance between adjacent word lines of the plurality of first word lines and adjacent word lines of the plurality of second word lines is less than a threshold based at least in part on the one or more first voids and the one or more second voids separating the plurality of first word lines from one another and the plurality of second word lines from one another.

14. The apparatus of claim 11 , wherein the one or more first voids and the one or more second voids enclose a gaseous material.

15. The apparatus of claim 11 , wherein at least one void of the one or more first voids is interconnected with at least one void of the one or more second voids.

16. The apparatus of claim 11 , wherein:

a pillar of the plurality of pillars comprises a conductive material and is configured for accessing a memory cell of the plurality of memory cells, and

a pier of the plurality of piers comprises a second dielectric material and is configured to support the memory array.

17. The apparatus of claim 11 , wherein:

the one or more first voids are enclosed at least in part by the plurality of first word lines, first sidewalls of the plurality of pillars, and first sidewalls of the plurality of piers, and

the one or more second voids are enclosed at least in part by the plurality of second word lines, second sidewalls of the plurality of pillars, and second sidewalls of the plurality of piers.

18. The apparatus of claim 11 , wherein the plurality of memory cells are separated from one another by the one or more first voids, or the one or more second voids, or some combination of both.