Compute optimizations for low precision machine learning operations
Embodiments described herein provide a graphics processor that can perform a variety of mixed and multiple precision instructions and operations. One embodiment provides a streaming multiprocessor that can concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for each of multiple instructions. The streaming multiprocessor can perform concurrent integer and floating-point operations and includes a mixed precision core to perform operations at multiple or mixed precisions and dynamic ranges.
1. A graphics processor comprising:
a memory device;
a compressor to compress data to be written to the memory device; and
a streaming multiprocessor coupled with the memory device, the streaming multiprocessor to concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for multiple instructions;
wherein the multiple instructions include a first instruction to cause a first portion of the streaming multiprocessor to perform a floating-point operation on multiple floating-point input operands and a second instruction to cause a second portion of the streaming multiprocessor to perform an integer operation on multiple integer operands, the first instruction to execute concurrently with the second instruction; and
wherein the streaming multiprocessor includes a mixed precision core to perform operations for a third instruction of the multiple instructions, the mixed precision core to perform a first operation of the third instruction at a first precision and a second operation of the third instruction at a second precision, the first operation of the third instruction includes a multiply performed on 16-bit floating-point input and the second operation of the third instruction includes an accumulate performed on input that includes a 32-bit floating-point input.
2. The graphics processor as in claim 1 , wherein the 16-bit floating-point input includes a half-precision floating-point input.
3. The graphics processor as in claim 1 , wherein the mixed precision core is to perform operations for a fourth instruction of the multiple instructions, the fourth instruction to cause the mixed precision core to perform a third operation on 8-bit integer input and a fourth operation on input that includes a 32-bit integer input.
4. The graphics processor as in claim 1 , further comprising a level-2 (L2) cache coupled with the compressor.
5. The graphics processor as in claim 4 , wherein the compressor is to losslessly compress the data to be written to the memory device.
6. The graphics processor as in claim 4 , wherein the compressor is to decompress data to be read from the memory device.
7. The graphics processor as in claim 6 , wherein the memory device is a high-bandwidth memory (HBM) device.
8. A method comprising:
decoding a first instruction via an instruction decoder of a graphics processor, the first instruction decoded into a first decoded instruction, wherein the graphics processor includes a streaming multiprocessor coupled to a memory device and a compressor to compress data to be written to the memory device, and the streaming multiprocessor includes a single instruction, multiple thread (SIMT);
executing multiple threads associated with the first decoded instruction via the streaming multiprocessor, wherein the first decoded instruction causes a first portion of the streaming multiprocessor to perform a floating-point operation on multiple floating-point input operands;
decoding a second instruction via the instruction decoder of the graphics processor into a second decoded instruction;
executing multiple threads associated with the second decoded instruction via the streaming multiprocessor, wherein the second decoded instruction causes a second portion of the streaming multiprocessor to perform an integer operation on multiple integer operands and the first decoded instruction executes concurrently with the second decoded instruction;
decoding a third instruction via the instruction decoder of the graphics processor into a third decoded instruction; and
executing multiple threads associated with the third decoded instruction via a mixed precision core of the streaming multiprocessor, wherein the mixed precision core performs a first operation of the third decoded instruction using a first number of bits and a second operation of the third decoded instruction using a second number of bits, the first operation of the third decoded instruction includes a multiply operation performed on 16-bit floating-point input and the second operation of the third decoded instruction includes an accumulate operation performed on input that includes a 32-bit floating-point input.
9. The method as in claim 8 , wherein the third instruction is a floating-point instruction, the first number of bits is associated with a first floating-point precision, and the second number of bits is associated with a second floating-point precision.
10. The method as in claim 8 , wherein the 16-bit floating-point input includes a half-precision floating-point input.
11. The method as in claim 8 , further comprising:
decoding a fourth instruction via the instruction decoder of the graphics processor into a fourth decoded instruction; and
executing multiple threads associated with the fourth decoded instruction via a mixed precision core of the streaming multiprocessor.
12. The method as in claim 11 , wherein the fourth instruction is an integer instruction, the first number of bits is associated with a first representable range of integer values, and the second number of bits is associated with a second representable range of integer values.
13. The method as in claim 12 , further comprising performing a first operation of the fourth decoded instruction on 8-bit integer input and performing a second operation of the fourth decoded instruction on input including a 32-bit integer input.
14. The method as in claim 13 , wherein the first operation of the fourth decoded instruction includes a multiply and the second operation of the fourth decoded instruction includes an accumulate.
15. The method as in claim 8 , further comprising compressing data associated with the first instruction, second instruction, or third instruction before writing the data to the memory device.
16. The method as in claim 15 , further comprising losslessly compressing the data associated with the first instruction, second instruction, or third instruction before writing the data to the memory device.
17. The method as in claim 8 , further comprising decompressing data associated with the first instruction, second instruction, or third instruction after reading the data from the memory device.
18. A graphics processing system comprising:
a system interface coupled with an interconnect fabric;
a graphics memory device coupled with the interconnect fabric;
a compressor to compress data to be written to the graphics memory device; and
a streaming multiprocessor coupled with the graphics memory device, the streaming multiprocessor to concurrently execute multiple thread groups, wherein the streaming multiprocessor includes a single instruction, multiple thread (SIMT) architecture and the streaming multiprocessor is to execute multiple threads for multiple instructions;
wherein the multiple instructions include a first instruction to cause a first portion of the streaming multiprocessor to perform a floating-point operation on multiple floating-point input operands and a second instruction to cause a second portion of the streaming multiprocessor to perform an integer operation on multiple integer operands, the first instruction to execute concurrently with the second instruction; and
wherein the streaming multiprocessor includes a mixed precision core to perform operations for a third instruction of the multiple instructions, the mixed precision core to perform a first operation of the third instruction at a first precision and a second operation of the third instruction at a second precision, the first operation of the third instruction includes a multiply performed on 16-bit floating-point input and the second operation of the third instruction includes an accumulate performed on input that includes a 32-bit floating-point input.
19. The graphics processing system as in claim 18 , wherein the graphics memory device is a high-bandwidth memory (HBM) device.
20. The graphics processing system as in claim 18 , wherein the third instruction is a floating-point instruction, the mixed precision core is to perform the first operation with a first number of bits to enable the first precision and perform the second operation with a second number of bits to enable the second precision, wherein the first precision and the second precision are floating-point precisions.
21. The graphics processing system as in claim 18 , wherein the 16-bit floating-point input includes a half-precision floating-point input.
22. The graphics processing system as in claim 18 , further comprising a level-2 (L2) cache coupled with the compressor.
23. The graphics processing system as in claim 22 , wherein the compressor is to losslessly compress the data to be written to the graphics memory device.
24. The graphics processing system as in claim 22 , wherein the compressor is to decompress data to be read from the graphics memory device.
25. The graphics processing system as in claim 18 , wherein the mixed precision core is to perform operations for a fourth instruction of the multiple instructions and the fourth instruction is an integer instruction.
26. The graphics processing system as in claim 25 , wherein the mixed precision core is to perform a first operation of the fourth instruction with a first number of bits to represent a first range of integer values and perform the second operation with a second number of bits to represent a second range of integer values.
27. The graphics processing system as in claim 26 , wherein the mixed precision core is to perform the first operation of the fourth instruction on 8-bit integer input and a second operation of the fourth instruction on input including a 32-bit integer input.
28. The graphics processing system as in claim 27 , wherein the first operation of the fourth instruction includes a multiply and the second operation of the fourth instruction includes an accumulate.
29. The graphics processor as in claim 3 , wherein the first operation of the fourth instruction includes a multiply and the second operation of the fourth instruction includes an accumulate.