IP Library Granted Patent US 12,148,724
Granted Patent B2
US 12,148,724 · App. 17/727,277 · Granted Nov 19, 2024

Package with built-in electronic components and electronic device

Inventors: Yukiko Oshikubo (Atsugi, JP); Yoshihiro Nakata (Atsugi, JP)
Assignee: FUJITSU LIMITED
H01L24/08H01L23/5226H01L23/5283H01L24/16H01L2224/0801H01L2224/08056H01L2224/08059H01L2224/16227H01L2224/16238H01L2924/35121
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Quick Facts
Patent No.
US 12,148,724
App. No.
17/727,277
Granted
Nov 19, 2024
Kind
B2
Abstract

A package with built-in electronic components that is to be soldered to an electronic circuit board includes: an insulating layer; an electronic component provided on one surface of the insulating layer; and a pad which is electrically connected to the electronic component and in which a plurality of openings that extend from a first surface of the pad in contact with a solder bump to the insulating layer are formed, wherein an area of the plurality of openings at the first surface is larger than an area of the plurality of openings at a second surface of the pad, which is an opposite surface to the first surface and is in contact with the insulating layer.

Claims (12)

1. A package with built-in electronic components that is to be soldered to an electronic circuit board, comprising:

an insulating layer;

an electronic component provided on one surface of the insulating layer; and

a pad which is electrically connected to the electronic component and in which a plurality of openings that extend from a first surface of the pad in contact with a solder bump to the insulating layer are formed, wherein an area of the plurality of openings at a second surface of the pad, which is an opposite surface to the first surface and is in contact with the insulating layer, is smaller than an area of the plurality of openings at the first surface.

2. The package with built-in electronic components according to claim 1 , wherein the plurality of openings have a stepped structure in a depth direction.

3. The package with built-in electronic components according to claim 1 , wherein the plurality of openings are formed deeper than a surface of the insulating layer that contacts the second surface.

4. The package with built-in electronic components according to claim 1 , wherein a ratio of an area occupied by the plurality of openings on the first surface is at least 0.3% and no greater than 30%.

5. The package with built-in electronic components according to claim 1 , wherein the plurality of openings are circular when viewed from above the first surface.

6. The package with built-in electronic components according to claim 1 , wherein the plurality of openings have at least two different sizes in a depth direction.

7. An electronic device comprising:

an electronic circuit board; and

a package with built-in electronic components that is joined to the electronic circuit board by a solder bump and includes: an insulating layer; an electronic component provided on one surface of the insulating layer; and a pad which is electrically connected to the electronic component and in which a plurality of openings that extend from a first surface of the pad in contact with the solder bump to the insulating layer are formed, wherein an area of the plurality of openings at a second surface of the pad, which is an opposite surface to the first surface and is in contact with the insulating layer, is smaller than an area of the plurality of openings at the first surface.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2026
From: FUJITSU LIMITED
To: 1FINITY INC.
Reel/Frame 074197/0244 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2022
From: OSHIKUBO, YUKIKO; NAKATA, YOSHIHIRO
To: FUJITSU LIMITED
Reel/Frame 059683/0775 →
Priority Claims (1)
JP 2021-129762 · Aug 6, 2021 · national
Continuity (1)
Related Publication 20230044252A1 · Feb 9, 2023