Computational memory with zero disable and error detection
A processing element includes an input zero detector to detect whether the input from the neighbor processing element contains a zero. When the input from the neighbor processing element contains the zero, a zero disable circuit controls the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the arithmetic logic unit for the operation. A controller of an array of processing elements adds a row of error-checking values to a matrix of coefficients, each error-checking value of the row of error-checking values being a negative sum of a respective column of the matrix of coefficients. The controller controls a processing element to perform an operation with the matrix of coefficients and an input vector to accumulate a result vector. Owing to the error-checking values, when a sum of elements of the result vector is non-zero, an error is detected.
1. A processing device comprising:
an array of processing elements, each processing element including logic to perform an operation in response to input to the logic being changed, each processing element connected to memory to store data for the operation;
interconnections among the array of processing elements to provide direct communication among neighboring processing elements of the array of processing elements, wherein a processing element of the array of processing elements is connected to a neighbor processing element via an input selector to selectively take output of the neighbor processing element as input to the processing element for the operation;
wherein the processing element further includes:
an input zero detector to detect whether the input from the neighbor processing element contains zero; and
a zero disable circuit connected to the input zero detector, wherein when the input from the neighbor processing element contains zero, the zero disable circuit is to control the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the logic to prevent the logic unit from performing the operation.
2. The processing device of claim 1 , wherein:
the input zero detector is further to detect whether the respective data of the memory contains zero; and
the zero disable circuit is to control the input from the neighbor processing element and respective data of the memory to both appear as unchanged to the logic for the operation, when either or both the input from the neighbor processing element or the respective data of the memory contains zero.
3. The processing device of claim 1 , wherein the logic includes cascading logic that is trigged by a change of input.
4. The processing device of claim 3 , wherein the logic includes an arithmetic logic unit.
5. The processing device of claim 1 , wherein the zero disable circuit includes a transparent latch, wherein an input to the transparent latch is connected to the memory, wherein the transparent latch latches the respective data of the memory if the respective data or the input from the neighbor processing element contains zero.
6. The processing device of claim 1 , wherein the zero disable circuit includes a register to store the input from the neighbor processing element, wherein the register does not latch the input value from the neighbor processing element if the input from the neighbor processing element or the respective data of the memory contains zero, and wherein the register latches the input value from the neighbor processing element if the input from the neighbor processing element does not contain zero.
7. The processing device of claim 6 , wherein the zero disable circuit includes a shadow register to transfer the input value from the neighbor processing element to a next neighbor processing element, wherein the shadow register has a path parallel to the register, wherein the shadow register latches the input value from the neighbor processing element if the input value from the neighbor processing element or the memory contains zero.