MULTI-PROCESSOR, MULTI-DOMAIN, MULTI-PROTOCOL, CACHE COHERENT, SPECULATION AWARE SHARED MEMORY AND INTERCONNECT
A device includes an interconnect and a plurality of devices connected to the interconnect. The plurality of devices includes a first interface connected to the interconnect and a second interface connected to the interconnect. The plurality of devices further includes a first memory bank connected to the interconnect and a second memory bank connected to the interconnect. The plurality of devices further includes an external memory interface connected to the interconnect and a controller configured to establish virtual channels among the plurality of devices connected to the interconnect.
1 . A method comprising:
receiving, at a controller, a memory request associated with an address of a data element;
determining, by the controller, a physical memory address associated with the address;
determining, by the controller, a tag associated with the physical memory address;
applying, by the controller, the tag to a cache tag bank to determine a cache tag result and a memory bank result; and
determining, by the controller, based on the cache tag result and the memory bank result whether to access a cached value of the data element or access the data element at the physical memory address of the data element.
2 . The method of claim 1 , wherein:
the memory request is received by an arbitration and data path manager of the controller.
3 . The method of claim 1 , wherein:
the address is a virtual address; and
the controller is configured to determine the physical memory address from the virtual address.
4 . The method of claim 1 , wherein:
the controller determines the tag by masking out one or more least significant bits of the physical memory address.
5 . The method of claim 1 , wherein:
an entry in the cache tag bank corresponds to an entry in a filter bank and an entry in a memory bank.
6 . The method of claim 1 , wherein:
the cache tag result includes a stored first value for the tag; and
the memory bank result includes a stored second value for the tag.
7 . The method of claim 6 , wherein:
the controller determines whether to issue snoop requests based on the cache tag result.
8 . The method of claim 6 , wherein:
the cache tag result includes a first status indicator associated with the stored first value for the tag; and
the memory bank result includes a second status indicator associated with the stored second value for the tag.
9 . A controller comprising:
a cache tag bank;
a memory bank; and
a snoop filter coupled to the cache tag bank and the memory bank by a cache line,
wherein the cache line includes:
a cache tag address associated with a data element;
a state of the cache tag address; and
a value of the memory bank associated with the cache tag address.
10 . The controller of claim 9 , wherein:
an entry in the snoop filter corresponds to an entry in the cache tag bank and an entry in the memory bank.
11 . The controller of claim 9 , wherein:
the state of the cache tag address indicates a cache of a master peripheral stores a value associated with cache tag address.
12 . The controller of claim 9 , wherein:
the state of the cache tag address includes one of shared, unique, invalid, modified, owned, and exclusive.
13 . A device comprising:
memory;
a controller coupled to the memory, wherein the controller is configured to:
receive a memory request associated with an address of a data element;
determine a physical memory address associated with the address;
determine a tag associated with the physical memory address;
apply the tag to a cache tag bank to determine a cache tag result and a memory bank result; and
determine, based on the cache tag result and the memory bank result, whether to access a cached value of the data element or access the data element at the physical memory address in the memory of the data element.
14 . The device of claim 13 , wherein:
the memory request is received by an arbitration and data path manager of the controller.
15 . The device of claim 13 , wherein:
the address is a virtual address; and
the controller is configured to determine the physical memory address from the virtual address.
16 . The device of claim 13 , wherein:
the controller determines the tag by masking out one or more least significant bits of the physical memory address.
17 . The device of claim 13 , wherein:
an entry in the cache tag bank corresponds to an entry in a filter bank and an entry in a memory bank.
18 . The device of claim 13 , wherein:
the cache tag result includes a stored first value for the tag; and
the memory bank result includes a stored second value for the tag.
19 . The device of claim 18 , wherein:
the controller determines whether to issue snoop requests based on the cache tag result.
20 . The device of claim 18 , wherein:
the cache tag result includes a first status indicator associated with the stored first value for the tag; and
the memory bank result includes a second status indicator associated with the stored second value for the tag.