Direct-drive D-mode GaN half-bridge power module
View Patent ↗A protected direct-drive depletion-mode (D-mode) GaN semiconductor half-bridge power module is disclosed. Applications include high power inverter applications, such as 100 kW to 200 kW electric vehicle traction inverters, and other motor drives. The high-side switch is a normally-on D-mode GaN semiconductor power switch Q 1 in series with a normally-off LV Si MOSFET power switch M 1 and the low-side switch is a normally on D-mode GaN semiconductor power switch Q 2 . The gates of both Q 1 and Q 2 are directly driven. M 1 in series with Q 1 provides a high-side switch which is a normally-off device for start-up and fail-safe protection. M 1 may also be used for current sensing and overcurrent protection. For example, a control circuit determines an operational mode of M 1 responsive to a UVLO signal and a voltage sense signal indicative of an overcurrent event. Examples of single phase and three-phase half-bridge modules and driver circuits are described.
1. A direct drive D-mode half-bridge power module comprising a high-side switch and a low-side switch connected in series, wherein the high-side switch is a D-mode normally-on GaN transistor switch (Q 1 ) in series with an E-mode normally-off Si MOSFET switch (M 1 ) and the low-side switch is a D-mode normally-on GaN transistor switch (Q 2 ), wherein gates of the D-mode normally-on GaN transistor switches Q 1 and Q 2 are directly driven, and the gate of E-mode normally-off Si MOSFET M 1 is directly driven by a control signal, wherein M 1 acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition.
2. The direct drive D-mode half-bridge power module of claim 1 , comprising a control circuit which determines the operational mode of M 1 responsive to an undervoltage lock-out (UVLO) signal and a voltage sense signal indicative of an overcurrent event.
3. The direct drive D-mode half-bridge power module of claim 2 , wherein the control circuit operates so that: M 1 is OFF during start-up until UVLO is off, M 1 is ON for normal operation; M 1 is turned-off during a fault condition if UVLO is turned-on; and if overcurrent protection (OCP) is triggered, M 1 is ON and Q 1 and Q 2 are turned-off.
4. A traction inverter comprising a multi-phase motor driver, wherein each phase leg comprises a half-bridge module as defined in claim 1 .
5. A method of operation of a half-bridge module as defined in claim 1 , wherein a control circuit is configured to determine an operational mode of M 1 responsive to an undervoltage lock-out (UVLO) signal and a voltage sense signal indicative of an overcurrent event, the control circuit operating so that: M 1 is OFF during start-up until UVLO is off; M 1 is ON for normal operation; M 1 is turned-off during a fault condition if UVLO is turned-on; and if overcurrent protection (OCP) is triggered, M 1 is ON and Q 1 and Q 2 are turned-off.
6. A power semiconductor switching device comprising:
a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein:
the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q 1 ) is connected in series with a normally-off Si MOSFET switch (M 1 ), the source of Q 1 being connected to the drain of M 1 ;
the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q 2 );
wherein gates of the D-mode normally-on GaN transistor switches Q 1 or Q 2 are directly driven, and the gate of the E-mode normally-off Si MOSFET M 1 is directly driven by a control circuit, wherein M 1 acts as a protection FET to hold the high-side switch in an off-state during start-up and during a fault condition; and
the control circuit is configured to determine an operational mode of M 1 responsive to an undervoltage lock-out (UVLO) signal and a voltage sense signal indicative of an overcurrent event, the control circuit operating so that: M 1 is OFF during start-up until UVLO is off; M 1 is ON for normal operation; M 1 is turned-off during a fault condition if UVLO is turned-on; and if overcurrent protection (OCP) is triggered, M 1 is ON and Q 1 and Q 2 are turned-off.
7. A power semiconductor switching device comprising:
a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein
the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q 1 ) is connected in series with a normally-off Si MOSFET switch (M 1 ), the source of Q 1 being connected to the drain of M 1 ;
the low side switch is a normally-on switch, comprising a second normally-on GaN transitory switch (Q 2 ); and
Q 1 has a source, a drain and a gate, wherein the drain of Q 1 is connected to the high voltage DC bus and the source of Q 1 is connected to a drain of M 1 , and the gate of Q 1 is connected to a first gate drive terminal for directly driving the gate of Q 1 ; the source of M 1 is connected to the switching node, a gate of M 1 is connected to an enable (control) terminal for directly driving the gate of the M 1 ; a high-side ground terminal is connected to the source of M 1 ; and a voltage sense terminal is connected to a common point between the source of Q 1 and the drain of M 1 ; and
Q 2 has a source, a drain and a gate, the drain of Q 2 is connected to the switching node and the source of Q 2 is connected to the low voltage DC bus, and the gate of Q 2 is connected to a second gate drive terminal for directly driving the gate of Q 2 ; and a low-side ground terminal is connected to the source of Q 2 .
8. The power semiconductor switching device of claim 7 wherein: M 1 acts as a protection FET to hold the high-side switch in an off-state during start-up and a fault condition.
9. The power semiconductor switching device of claim 7 , wherein:
Q 1 comprises a plurality of GaN transistors connected in parallel;
M 1 comprises a plurality of Si MOSFETs connected in parallel;
Q 2 comprises a plurality of GaN transistors connected in parallel.
10. The power semiconductor switching device of claim 7 , wherein:
Q 1 comprises a plurality of GaN HEMTs connected in parallel;
M 1 comprises a plurality of Si MOSFET connected in parallel;
Q 2 comprises a plurality of GaN HEMTs connected in parallel.
11. The power semiconductor switching device of claim 6 wherein:
Q 1 comprises a plurality of GaN transistors connected in parallel;
M 1 comprises a plurality of Si MOSFETs connected in parallel;
Q 2 comprises a plurality of GaN transistors connected in parallel.
12. A power semiconductor switching device comprising:
a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus and a low voltage DC bus, the high side switch being connected to the low side switch at a switching node, wherein:
the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q 1 ) is connected in series with a normally-off Si MOSFET switch (M 1 ), the source of Q 1 being connected to the drain of M 1 ; and
the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q 2 );
and
a half-bridge driver circuit comprising:
a high-side driver for directly driving a gate of Q 1 ;
a low-side driver for directly driving a gate of Q 2 ;
wherein the high-side driver and the low-side driver are driven by PWM input signals INH and INL respectively; and
a control circuit for driving M 1 , wherein the control circuit comprises a gate driver for providing an enable (control) signal for directly driving the gate of M 1 in response to a gate input signal PGOOD,
the control circuit having a voltage sense input Vsen from a voltage sense terminal connected to a node between the source of Q 1 and the drain of M 1 ,
circuitry for receiving an undervoltage lock-out (UVLO) signal, and determining a power status and operational mode for M 1 ,
circuitry for comparing the voltage sense input Vsen to a reference overcurrent protection (OCP) limit voltage V OCP_limit , wherein said enable signal provides that
M 1 is OFF during start-up until UVLO is off;
M 1 is ON for normal operation;
M 1 is turned-off during a fault condition if UVLO is turned-on;
and
if OCP is triggered, M 1 is ON and Q 1 and Q 2 are turned-off.
13. The power semiconductor switching device of claim 12 comprising:
a high-side switch and a low-side switch connected in series in a half-bridge configuration, between a high voltage DC bus (rail) and a low voltage DC bus (rail), the high side switch being connected to the low side switch at a switching node, wherein:
the high-side switch is a normally-off switch wherein a first normally-on GaN transistor switch (Q 1 ) is connected in series with a normally-off Si MOSFET switch (M 1 ); and
the low side switch is a normally-on switch, comprising a second normally-on GaN transistor switch (Q 2 ); wherein:
Q 1 has a source, a drain and a gate, wherein the drain of Q 1 is connected to the high voltage DC bus and the source of Q 1 is connected to a drain of M 1 , and the gate of Q 1 is connected to a first gate drive terminal for directly driving the gate of Q 1 ; the source of M 1 is connected to the switching node, a gate of M 1 is connected to an enable (control) terminal for directly driving the gate of the M 1 ; a high-side ground terminal is connected to the source of M 1 ; and a voltage sense terminal is connected a common point between the source of Q 1 and the drain of M 1 ; and
Q 2 has a source, a drain and a gate, the drain of Q 2 is connected to the switching node and the source of Q 2 is connected to the low voltage DC bus, and the gate of Q 2 is connected to a second gate drive terminal for directly driving the gate of Q 2 ; and a low-side ground terminal is connected to the source of Q 2 ;
a half-bridge driver circuit comprising:
a high-side driver for directly driving a gate of Q 1 ;
a low-side driver for directly driving a gate of Q 2 ;
wherein the high-side driver and the low-side driver are driven by PWM input signals INH and INL respectively; and
a control circuit for driving M 1 , wherein the control circuit comprises a gate driver for providing an enable (control) signal for directly driving the gate of M 1 in response to a gate input signal PGOOD,
a voltage sense input Vsen from a voltage sense terminal connected to a node between the source of Q 1 and the drain of M 1 ,
a UVLO signal input, and circuitry for determining a power status and operational mode for M 1 ,
circuitry for comparing the voltage sense input Vsen to a reference OCP limit voltage V OCP_limit and triggering OCP if Vsen exceeds the OCP limit voltage;
wherein said enable signal provides that
M 1 is OFF during start-up until UVLO is off;
M 1 is ON for normal operation;
M 1 is turned-off during a fault condition if UVLO is turned-on;
and
if OCP is triggered, M 1 is ON and Q 1 and Q 2 are turned-off.