Clockless pulse width generation
Technologies are provided for generation of programmable pulse signals using inverse chaotic maps, without reliance on a clocking signal. Some embodiments of the technologies include an apparatus that can receive a sequence of bits having a defined number of bits, where the sequence of bits represent a desired continuous pulse signal having a programmable width in time-domain. The apparatus can also can receive a precursor continuous pulse signal having an arbitrary width in time-domain that fits within the dynamic range of the apparatus. The apparatus can generate the desired continuous pulse signal by transforming the precursor continuous pulse signal using the sequence of bits and an inverse chaotic map.
1. A method comprising:
receiving a first pulse, wherein a voltage of the first pulse is constant for a first duration;
generating, based on a first combination of a rising edge of a first indication and a rising edge of the first pulse, a rising edge of a second pulse; and
generating, based on a second combination of a falling edge of the first pulse and a predetermined delay, a falling edge of the second pulse, wherein the second pulse comprises the voltage that is constant for a second duration, wherein the second duration is based on a latch and the predetermined delay, wherein the predetermined delay is based on a time delay.
2. The method of claim 1 , wherein the first indication is a first bit.
3. The method of claim 1 , wherein the first indication is based on a sequence of bits.
4. The method of claim 1 , further comprising:
generating, based on a falling edge of the second pulse, a rising edge of a third pulse; and
generating, based on a first integration of the second pulse and a second integration of the second pulse, a falling edge of the third pulse.
5. The method of claim 4 , wherein the first integration is based on a first integrator circuit and the second integration is based on a second integrator circuit.
6. The method of claim 4 , wherein the generation of the falling edge of the third pulse comprises:
holding a peak voltage of the second integration; and
comparing the peak voltage of the second integration with a voltage of the first integration.
7. The method of claim 6 , wherein the voltage of the first integration comprises a negative slope.
8. The method of claim 6 , wherein the generation of the falling edge of the third pulse occurs when the peak voltage of the second integration is equal to the voltage of the first integration.
9. The method of claim 1 , wherein the first duration is based on the latch.
10. The method of claim 1 , wherein the rising edge of the first pulse is generated based on a falling edge of a third pulse, and wherein the falling edge of the first pulse is generated based on a first integration of the third pulse and a second integration of the third pulse.
11. The method of claim 10 , wherein the third pulse comprises the voltage that is constant for a third duration.
12. An apparatus comprising:
first circuitry comprising:
a first gate configured to generate, based on a first bit and a first pulse, a first output;
a time delay configured to generate, based on the first pulse, a second output; and
a latch configured to generate, based on the first output and the second output, a third output, wherein the third output is set according to the first output and reset according to the second output; and
second circuitry configured to:
generate, based on the third output and the second output, a fourth output;
generate, based on the third output being set, a rising edge of the fourth output; and
generate, based on a falling edge of the second output, a falling edge of the fourth output.
13. The apparatus of claim 12 , further comprising:
third circuitry comprising:
a first operational integrator having a first time constant configured to generate, based on the fourth output, a first integration;
a second operational integrator having a second time constant configured to generate, based on the fourth output, a second integration;
a comparator configured to generate, based on an intersection of a peak of the first integration and a voltage of the second integration, a fifth output; and
a second gate configured to:
generate, based on the falling edge of the fourth output, a rising edge of a second pulse, and
generate, based on the intersection, a falling edge of the second pulse.
14. An apparatus comprising:
first circuitry comprising:
a first operational integrator having a first time constant configured to generate, based on a first pulse, a first integration;
a second operational integrator having a second time constant configured to generate, based on the first pulse, a second integration;
a comparator configured to generate, based on an intersection of a peak of the first integration and a voltage of the second integration, a first output; and
a first gate configured to:
generate, based on a falling edge of the first pulse, a rising edge of a second pulse; and
generate, based on the intersection, a falling edge of the second pulse.
15. The apparatus of claim 14 , further comprising:
second circuitry comprising:
a second gate configured to generate, based on a first bit and the first output, a second output;
a time delay configured to generate, based on the first output, a third output; and
a latch configured to generate, based on the second output and the third output, a fourth output, wherein the fourth output is set according to the second output and reset according to the third output; and
third circuitry configured to:
generate, based on the fourth output and the third output, a fifth output;
generate, based on the fourth output being set, a rising edge of the fifth output; and
generate, based on a falling edge of the third output, a falling edge of the fifth output.