Semiconductor memory device and memory system including the same

1. A semiconductor memory device comprising:

a memory cell array comprising a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines; and

a cyclic redundancy check (CRC) engine configured to perform, during a memory operation on the memory cell array, operations comprising:

detecting an error in a main data and a system parity data received from a memory controller through a link, wherein the memory controller is external to the semiconductor memory device;

generating an error flag indicating whether the error that was detected corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data; and

transmitting the error flag to the memory controller.

2. The semiconductor memory device of claim 1 ,

wherein the CRC engine comprises a CRC generator and a CRC checker, and

wherein, during a write operation based on a write command from the memory controller, the CRC generator is configured to generate a first reference system parity data based on the main data from the memory controller, and the CRC checker is configured to determine a logic level of the error flag associated with the first type of error based on comparison of the system parity data and the first reference system parity data.

3. The semiconductor memory device of claim 2 , wherein the CRC checker is configured to transmit the error flag having a first logic level to the memory controller in response to the system parity data being different from the first reference system parity data.

4. The semiconductor memory device of claim 2 , wherein the CRC checker comprises:

a first buffer configured to store the system parity data;

a second buffer configured to store the first reference system parity data;

a comparator configured to receive the system parity data from the first buffer and receive the first reference system parity data from the second buffer and configured to generate a syndrome data by comparing the system parity data with the first reference system parity data; and

an error flag generator configured to generate the error flag based on the syndrome data and determine the logic level of the error flag based on the syndrome data.

5. The semiconductor memory device of claim 2 , further comprising:

an on-die error correction code (ECC) engine,

wherein the on-die ECC engine comprises an ECC encoder, and

wherein the ECC encoder, during the write operation, is configured to perform operations comprising:

performing an ECC encoding operation on the main data and the system parity data to generate a parity data for correcting an error generated in the memory cell array; and

storing the main data, the system parity data, and the parity data in a target page of the memory cell array.

6. The semiconductor memory device of claim 5 ,

wherein the on-die ECC engine is configured to perform operations comprising:

storing the main data and the system parity data in a normal cell region of the target page; and

storing the system parity data in a redundancy cell region of the target page.

7. The semiconductor memory device of claim 5 ,

wherein the on-die ECC engine further comprises an ECC decoder, and

wherein the ECC decoder, during a read operation based on a read command from the memory controller, is configured to perform operations comprising:

reading the main data, the system parity data, and the parity data from the target page;

performing an ECC decoding operation on the main data and the system parity data using the parity data to correct a correctable error in the main data and the system parity data; and

transmitting the main data and the system parity data to the memory controller.

8. The semiconductor memory device of claim 7 ,

wherein the CRC generator is configured to generate a second reference system parity data based on the main data received from the ECC decoder, and

wherein the CRC checker is configured to determine a logic level of the error flag associated with the second type of error based on comparison of the system parity data and the second reference system parity data.

9. The semiconductor memory device of claim 8 , wherein the CRC checker is configured to transmit the error flag having a first logic level to the memory controller in response to the system parity data being different from the second reference system parity data and indicating that the main data and the system parity data include uncorrectable errors associated with the volatile memory cells.

10. The semiconductor memory device of claim 7 , wherein the ECC decoder comprises:

a syndrome generation circuit configured to generate a syndrome data based on the main data and the system parity data read from the target page;

an error locator configured to generate an error position signal indicating a position of at least one error bit in the main data and the system parity data; and

a data corrector configured to correct the correctable error in the main data and the system parity data based on the error position signal.

11. The semiconductor memory device of claim 2 ,

wherein the CRC generator is configured to generate the first reference system parity data by performing a CRC operation on the main data, and

wherein semiconductor memory device is further configured to determine that a non-single-bit error in the main data is generated during data transmission on the link or is generated in the plurality of volatile memory cells in the memory cell array.

12. The semiconductor memory device of claim 2 , wherein the semiconductor memory device is configured to receive the system parity data from the memory controller through a first dedicated pin and is configured to transmit the error flag to the memory controller through a second dedicated pin different from the first dedicated pin.

13. A memory system comprising:

a semiconductor memory device; and

a memory controller configured to communicate with the semiconductor memory device and configured to control the semiconductor memory device,

wherein the semiconductor memory device comprises:

a memory cell array comprising a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines;

a first cyclic redundancy check (CRC) engine, in a memory operation on the memory cell array, configured to perform operations comprising:

detecting an error in a main data and a system parity data received from the memory controller through a link; and

generating a first error flag indicating whether the error that was detected corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data; and

an on-die error correction code (ECC) engine configured to perform an ECC encoding operation on the main data and the system parity data and configured to perform an ECC decoding operation on the main data and the system parity data to correct a correctable error in the main data.

14. The memory system of claim 13 ,

wherein the memory controller comprises a second CRC engine and a central processing unit (CPU) configured to control operation of the memory controller,

wherein the second CRC engine, during a write operation on the semiconductor memory device, is configured to generate the system parity data based on the main data and is configured to transmit the main data and the system parity data to the semiconductor memory device,

wherein the first CRC engine comprises a CRC generator and a CRC checker, and

wherein, during the write operation based on a write command from the memory controller, the CRC generator is configured to generate a first reference system parity data based on the main data, and the CRC checker is configured to transmit, to the memory controller, the first error flag having a first logic level indicating that the first type of error occurs based on comparing the system parity data with the first reference system parity data.

15. The memory system of claim 14 , wherein the memory controller is configured to transmit the main data and the system parity data to the semiconductor memory device in response to receiving the first error flag having the first logic level.

16. The memory system of claim 14 ,

wherein the on-die ECC engine comprises an ECC encoder and the ECC decoder,

wherein the ECC encoder, during the write operation, is configured to perform the ECC encoding operation on the main data and the system parity data to generate a parity data and is configured to store the main data, the system parity data, and the parity data in a target page of the memory cell array, and

wherein the ECC decoder, during a read operation based on a read command from the memory controller, is configured to perform operations comprising:

reading the main data, the system parity data, and the parity data from the target page;

performing the ECC decoding operation on the main data and the system parity data using the parity data to correct a correctable error in the main data and the system parity data; and

transmitting the main data and the system parity data to the memory controller.

17. The memory system of claim 16 ,

wherein the CRC generator is configured to generate a second reference system parity data based on the main data received from the ECC decoder, and

wherein the CRC checker is configured to transmit, to the memory controller, the first error flag having a first logic level indicating that the second type of error occurs based on comparing the system parity data with the second reference system parity data.

18. The memory system of claim 14 ,

wherein the second CRC engine comprises a CRC generator and a CRC checker,

wherein the CRC generator, during a read operation, is configured to generate a reference system parity data based on the main data received from the semiconductor memory device, and

wherein the CRC checker is configured to generate a second error flag associated with the first type of error based on comparing the system parity data with the reference system parity data and is configured to determine a logic level of the second error flag based on the comparing.

19. The memory system of claim 18 , wherein the CPU is configured to determine that an error in the main data is associated with either the first type of error or the second type of error based on the first error flag and the second error flag.

20. A semiconductor memory device comprising:

a memory cell array comprising a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines; and

a cyclic redundancy check (CRC) engine, during a memory operation on the memory cell array, configured to perform operations comprising:

detecting an error in a main data and a system parity data received from a memory controller through a link, wherein the memory controller is external to the semiconductor memory device; and

generating an error flag indicating whether the error that was detected corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data; and

an on-die error correction code (ECC) engine configured to perform an ECC encoding operation on the main data and the system parity data and configured to perform an ECC decoding operation on the main data and the system parity data,

wherein the CRC engine comprises a CRC generator and a CRC checker, and

wherein, during the memory operation based on a command from the memory controller, the CRC generator is configured to generate a first reference system parity data based on the main data provided from the memory controller, and

wherein the CRC checker is configured to determine a logic level of the error flag associated with one of the first type of error or the second type of error based on comparison of the system parity data and the first reference system parity data.