MRAM access coordination systems and methods via pipeline in parallel
Embodiments of the present invention facilitate efficient and effective increased memory cell density configuration. In one embodiment, a memory system comprises: an array of addressable memory cells, wherein the addressable memory cells of the array comprise magnetic random access memory (MRAM) cells and wherein further the array is organized into a plurality of banks; an engine configured to control access to the addressable memory cells organized into the plurality of banks; and a pipeline configured to perform access control and communication operations between the engine and the array of addressable memory cells. At least a portion of operations associated with accessing at least a portion of one of the plurality of memory banks via the pipeline are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing at least another portion of one of the plurality of memory banks via the pipeline.
1. A memory device configured to store information for a processor, the processor accessing the memory device via a memory controller, comprising:
an array of addressable memory cells, wherein said addressable memory cells of said array comprise magnetic random access memory (MRAM) cells and wherein further said array is organized into a plurality of memory banks, and wherein the memory controller is configured to operate in accordance with requirements corresponding to a different type of memory than said addressable memory cells comprising magnetic random access memory (MRAM) cells;
an engine configured to control access to said addressable memory cells organized into said plurality of banks; and
a plurality of pipelines configured to perform access control and communication operations between said engine and said plurality of memory banks of said array of addressable memory cells, wherein at least a portion of operations associated with accessing a first memory bank of said plurality of memory banks via a first pipeline of said plurality of pipelines are performed substantially concurrently or in parallel with at least a portion of operations associated with accessing a second memory bank of said plurality of memory banks via a second pipeline of said plurality of pipelines, wherein said operations associated with accessing the first and second memory banks of said plurality of memory banks are coordinated to compensate for differences in operational requirements of the memory controller and operational constraints of said array of addressable memory cells.
2. The memory device of claim 1 , wherein the substantially concurrent or parallel pipelines operations enable said array of addressable memory cells to meet data output response timing requirements of the memory controller operating in accordance with requirements corresponding to a different type of memory than said addressable memory cells comprising magnetic random access memory (MRAM) cells.
3. The memory device of claim 2 , wherein the substantially concurrent or parallel pipelines operations enable said array of addressable memory cells to meet data output response timing requirements of a dynamic random access memory (DRAM) controller accessing said addressable memory cells comprising magnetic random access memory (MRAM) cells.
4. The memory device of claim 2 , wherein said engine operates said plurality of pipelines to serve the first and second memory banks of said plurality of memory banks.
5. The memory device of claim 4 , wherein said first memory bank and said second memory bank are included in a memory bank group, wherein the engine serves the memory bank group.
6. The memory device of claim 1 , wherein the engine is configured to access at least a portion of said plurality of memory banks via a first one of said pipelines and to access at least another portion of said plurality of memory banks via a second one of said pipelines, substantially concurrently or in parallel.
7. The memory device of claim 1 , wherein with respect to the first memory bank having the first pipeline associated therewith, while said first pipeline is processing a first plurality of read and/or write operations to the first memory bank, but not yet finished, said second pipeline is operable to commence processing a second read and/or write operation to the second memory bank of said plurality of memory banks.