Memory arrays, and methods of forming memory arrays
View Patent ↗Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends along the stack. Conductive segments are along the wordline levels. Each of the conductive segments has, along a cross-section, first and second ends in opposing relation to one another. The conductive segments include gates and wordlines adjacent the gates. The wordlines encompass the second ends, and the gates have rounded (e.g., substantially parabolic) noses which encompass the first ends. Some embodiments include methods of forming integrated assemblies.
1. A method of forming an assembly, comprising:
forming a first opening through a stack of alternating first and second levels; the first levels comprising a first material, and the second levels comprising an insulative second material; the first levels comprising edges along the first opening;
rounding the edges of the first levels and forming charge-blocking material adjacent the rounded edges;
forming charge-storage material adjacent the charge-blocking material;
forming tunneling material adjacent the charge-storage material; and
forming channel material within the first opening and adjacent the tunneling material.
2. The method of claim 1 wherein the opening is a first opening, and further comprising
forming a second opening through the stack; and
after forming the second opening, removing the first material of the first levels to form cavities.
3. The method of claim 2 , further comprising forming conductive segments within the cavities, each of the conductive segments having gate regions having a rounded edge.
4. The method of claim 1 wherein the edges of the first levels are first edges; wherein the second levels have second edges along the opening; wherein the forming of the rounded edges of the first levels insets the second edges of the second levels to leave recesses between vertically-adjacent rounded edges of the first levels; and comprising forming an insulative third material within the recesses prior to forming the charge-blocking material.
5. The method of claim 4 wherein the second levels have thicknesses of a first dimension; and wherein the recesses have depths of a second dimension, with the second dimension at least about one-half of the first dimension.
6. The method of claim 1 wherein the first material comprises silicon nitride, and wherein at least some of the charge-blocking material comprises silicon oxynitride formed by oxidizing the rounded edges of the first levels.
7. The method of claim 1 wherein the rounded noses are substantially parabolic.