Using physical address proxies to handle synonyms when writing store data to a virtually-indexed cache
A microprocessor includes a virtually-indexed L1 data cache that has an allocation policy that permits multiple synonyms to be co-resident. Each L2 entry is uniquely identified by a set index and a way number. A store unit, during a store instruction execution, receives a store physical address proxy (PAP) for a store physical memory line address (PMLA) from an L1 entry hit upon by a store virtual address, and writes the store PAP to a store queue entry. The store PAP comprises the set index and the way number of an L2 entry that holds a line specified by the store PMLA. The store unit, during the store commit, reads the store PAP from the store queue, looks up the store PAP in the L1 to detect synonyms, writes the store data to one or more of the detected synonyms, and evicts the non-written detected synonyms.
1. A microprocessor, comprising:
a store queue;
a virtually-indexed first-level data cache that has an allocation policy that permits multiple synonyms to be co-resident in the first-level data cache;
a physically-indexed physically-tagged second-level set-associative cache, wherein each entry in the second-level cache is uniquely identified by a set index and a way number; and
a store unit configured to:
during execution of a store instruction that specifies store data and a store virtual address:
receive a store physical address proxy (PAP) for a store physical memory line address from an entry of the first-level data cache hit upon by the store virtual address, wherein the store physical memory line address is a translation of the store virtual address, wherein the store PAP comprises the set index and the way number of an entry of the second-level cache that holds a copy of a line of memory specified by the store physical memory line address; and
write the store PAP to an entry of the store queue allocated to the store instruction; and
during commit of the store instruction:
read the store PAP from the store queue;
lookup the store PAP in the first-level data cache to detect synonyms each of which holds a copy of the line of memory specified by the store physical memory line address for which the store PAP is a proxy;
write the store data to one or more of the detected synonyms; and
evict the detected synonyms to which the store data is not written.
2. The microprocessor of claim 1 , wherein the one or more of the detected synonyms to which the store data is written includes the entry of the first-level data cache hit upon by the store virtual address.
3. The microprocessor of claim 1 , wherein the evicted detected synonyms do not include the entry of the first-level data cache hit upon by the store virtual address.
4. The microprocessor of claim 1 , wherein the first-level data cache is also virtually-tagged.
5. The microprocessor of claim 1 ,
wherein the microprocessor has an inclusive allocation policy such that:
each cache line of memory allocated into the first-level data cache is also allocated into the second-level cache; and
when the second-level cache evicts the cache line, the second-level cache also causes the first-level data cache to evict the cache line.
6. The microprocessor of claim 1 , further comprising:
a PAP directory in which the store PAP is looked up to detect the synonyms;
wherein the first-level data cache is logically arranged as S sets and W ways; and
wherein the PAP directory is physically arranged as R rows and C columns, and wherein C is greater than W and R is less than S.
7. The microprocessor of claim 6 ,
wherein C=W*(2{circumflex over ( )}T); and
wherein T is a number of translated address bits of the store virtual address used to select a set of the S sets during a lookup of the store virtual address in the first-level cache.
8. The microprocessor of claim 7 ,
wherein R=W/(2{circumflex over ( )}T).
9. The microprocessor of claim 6 ,
wherein a first portion of the store PAP is used to select a row of the PAP directory during the lookup of the store PAP;
wherein a second portion of the store PAP not included in the first portion is a diminutive PAP (dPAP); and
wherein the dPAP is compared against a corresponding dPAP held in each entry in the selected row of the PAP directory during the lookup of the store PAP.
10. The microprocessor of claim 9 ,
wherein the first portion of the store PAP used to select a row of the PAP directory during the lookup of the store PAP includes only untranslated address bits of the set index of the second-level cache.
11. A method, comprising:
in a microprocessor comprising:
a store queue;
a virtually-indexed first-level data cache that has an allocation policy that permits multiple synonyms to be co-resident in the first-level data cache; and
a physically-indexed physically-tagged second-level set-associative cache, wherein each entry in the second-level cache is uniquely identified by a set index and a way number; and
during execution of a store instruction that specifies store data and a store virtual address:
receiving a store physical address proxy (PAP) for a store physical memory line address from an entry of the first-level data cache hit upon by the store virtual address, wherein the store physical memory line address is a translation of the store virtual address, wherein the store PAP comprises the set index and the way number of an entry of the second-level cache that holds a copy of a line of memory specified by the store physical memory line address; and
writing the store PAP to an entry of the store queue allocated to the store instruction; and
during commit of the store instruction:
reading the store PAP from the store queue;
looking up the store PAP in the first-level data cache to detect synonyms each of which holds a copy of the line of memory specified by the store physical memory line address for which the store PAP is a proxy;
writing the store data to one or more of the detected synonyms; and
evicting the detected synonyms to which the store data is not written.
12. The method of claim 11 , wherein the one or more of the detected synonyms to which the store data is written includes the entry of the first-level data cache hit upon by the store virtual address.
13. The method of claim 11 , wherein the evicted detected synonyms do not include the entry of the first-level data cache hit upon by the store virtual address.
14. The method of claim 11 , wherein the first-level data cache is also virtually-tagged.
15. The method of claim 11 ,
wherein the microprocessor has an inclusive allocation policy such that:
each cache line of memory allocated into the first-level data cache is also allocated into the second-level cache; and
when the second-level cache evicts the cache line, the second-level cache also causes the first-level data cache to evict the cache line.
16. The method of claim 11 ,
wherein the microprocessor further comprises:
a PAP directory in which the store PAP is looked up to detect the synonyms;
wherein the first-level data cache is logically arranged as S sets and W ways; and
wherein the PAP directory is physically arranged as R rows and C columns, and wherein C is greater than W and R is less than S.
17. The method of claim 16 ,
wherein C=W*(2{circumflex over ( )}T); and
wherein T is a number of translated address bits of the store virtual address used to select a set of the S sets during a lookup of the store virtual address in the first-level cache.
18. The method of claim 17 ,
wherein R=W/(2{circumflex over ( )}T).
19. The method of claim 16 ,
wherein a first portion of the store PAP is used to select a row of the PAP directory during the lookup of the store PAP;
wherein a second portion of the store PAP not included in the first portion is a diminutive PAP (dPAP); and
wherein the dPAP is compared against a corresponding dPAP held in each entry in the selected row of the PAP directory during the lookup of the store PAP.
20. The method of claim 19 ,
wherein the first portion of the store PAP used to select a row of the PAP directory during the lookup of the store PAP includes only untranslated address bits of the set index of the second-level cache.
21. A microprocessor, comprising:
a virtually-indexed first-level data cache that has an allocation policy that permits multiple synonyms to be co-resident in the first-level data cache;
a store unit configured to:
execute a store instruction that specifies store data and a store virtual address; and
during commit of the store instruction:
detect synonyms each of which holds a copy of a line of memory;
write the store data to one or more of the detected synonyms; and
evict the detected synonyms to which the store data is not written;
a store queue; and
a physically-indexed physically-tagged second-level set-associative cache, wherein each entry in the second-level cache is uniquely identified by a set index and a way number;
wherein the line of memory is specified by a store physical memory line address, wherein the store physical memory line address is a translation of the store virtual address; and
wherein the store unit is configured to:
during execution of the store instruction:
write a store physical address proxy (PAP) for the store physical memory line address to an entry of the store queue allocated to the store instruction, wherein the store PAP comprises the set index and the way number of an entry of the second-level cache that holds a copy of a line of memory specified by the store physical memory line address; and
during commit of the store instruction:
read the store PAP from the store queue; and
lookup the store PAP in the first-level data cache to detect the synonyms.