System and method for sending and receiving an ethernet frame
A control panel for a fire alarm system includes a microprocessor operable to send and receive data. The microprocessor has a serial peripheral interface with a master port and a slave port. A computing device has a Differential Manchester encoder configured to encode data received from the master port and a Differential Manchester decoder configured to decode frames and send the decoded data to the slave port. A method of sending and receiving data is also disclosed.
1 . A control panel for a fire alarm system, comprising:
a microcontroller operable to send and receive data in a form of Ethernet frames, the microcontroller including a physical layer port and a serial peripheral interface;
a FPGA (field programmable gate array), wherein the microcontroller is operable to receive variable size serial peripheral interface (SPI) signals including the data from the physical layer port and send variable size SPI signals to the FPGA via the serial peripheral interface which includes a master port and a slave port;
wherein the FPGA has a Differential Manchester encoder configured to encode data received from the master port of the serial peripheral interface and a Differential Manchester decoder;
a transceiver that receives encoded data from the FPGA, and wherein the Differential Manchester decoder is operable to:
receive Differential-Manchester-encoded signals via the transceiver;
decode encoded signals; and
transmit decoded signals to the slave port;
a wire connected to the control panel for carrying the data and wherein the transceiver is configured to enable communication over the wire; and
wherein the microcontroller and FPGA are operable to send and receive data at a rate of 1 Mbps over the wire in each direction for a rate of 2 Mbps total as a shared data path.
2 . The control panel of claim 1 , wherein the wire is a twisted pair wire.
3 . The control panel of claim 1 , wherein the microcontroller is operable to send and receive the data to and from the wire via the physical layer port.
4 . The control panel of claim 3 , wherein the physical layer port is an MII (media independent interface) port.
5 . The control panel of claim 1 , wherein the FPGA is programmed to perform Differential Manchester encoding and Differential Manchester decoding.
6 . The control panel of claim 1 , wherein the transceiver is configured to enable communication over the wire at rates of at least 1 Mbps.
7 . The control panel of claim 1 , wherein the master port and the slave port allow two-way communication between the microcontroller and FPGA.
8 . The control panel of claim 7 , wherein each of the master port and the slave port includes a data pin and a clock pin.
9 . The control panel of claim 8 , wherein the master port includes a select signal and the slave port includes a slave chip select, and when the select signal is an input, the serial peripheral interface is acting as a slave, and when the serial peripheral interface sends a select signal, the serial peripheral interface is acting as a master.
10 . The control panel of claim 9 , wherein when the master port sends data from Ethernet frames to the FPGA such that the serial peripheral interface is acting as the master, the select signal is held low for a duration of the Ethernet frames.
11 . The control panel of claim 10 , wherein the wire comprises a twisted pair wire connected to the control panel for carrying the data and wherein the transceiver is configured to enable communication over the twisted pair wire at rates of at least 1 Mbps, and wherein data is clocked to the FPGA on a falling, high-to-low edge of a clock pin signal, and as the data is received, a transmit select signal of the transceiver is held high, putting the transceiver in a transmit mode.
12 . The control panel of claim 11 , wherein the transceiver includes a receive select signal that is held low while the transceiver is in transmit mode.
13 . The control panel of claim 12 , wherein the data in the Ethernet frames is sent via the master port using a Direct Memory Access in the microcontroller.
14 . The control panel of claim 12 , wherein when the slave port receives data from the FPGA, the transmit select signal is held low and the receive select signal is held high so that the transceiver is in receive mode.
15 . The control panel of claim 14 , wherein a slave chip select signal of the slave port is held low for a duration of the Ethernet frames, and the Ethernet frames is received in the transceiver and then is clocked to the FPGA as a receive signal of the transceiver, and the data is clocked from the FPGA to the serial peripheral interface on falling, high-to-low edge of a clock signal.