Wafer level package
A fullcover package solution in combination with copper pillars or solder bumps and acoustic cavities is proposed to provide maximum usable design area compared to current thin film acoustic wafer level packages. Manufacturing can be done in a self-aligned interconnection process.
1 . A wafer level package, comprising:
a substrate (SU) having a functional layer and electric device structures (DS) realized in the functional layer, on the functional layer or under the functional layer;
a first package layer (PL 1 ) applied on the substrate, the first package layer defining cavities (CV) between the substrate and the first package layer, at least part of the device structures being arranged in the cavities;
a second package layer (PL 2 ) applied over a surface of the first package layer;
pads (PD) arranged on the substrate and connected to the device structures, a partial area of each pad forming a respective contact area that is not covered by the first package layer or the second package layer;
an interconnect structure (IS) deposited on each respective contact area and extending up to an interconnect height (h i ) over the substrate, the interconnect height being higher than a package height (h p ) of the first package layer and the second package layer over the substrate; and
solder caps (SC) disposed at a respective distal end of each respective interconnect structure.
2 . The wafer level package of claim 1 , wherein the first package layer is a rigid inorganic layer and wherein the second package layer is a polymer layer.
3 . The wafer level package of claim 1 ,
wherein a margin along at least one edge of the substrate excludes the second package layer, wherein at least some of the respective contact areas and the corresponding interconnection structures are fully enclosed by the second package layer, and wherein other contact areas are optionally situated at an edge (EPL 2 ) of the second package layer such that the other contact areas are only partially surrounded by the second package layer.
4 . The wafer level package of claim 1 , wherein cutouts in a selected package layer defines shapes of the respective contact areas, and wherein the selected package layer is chosen from first package layer, the second package layer or an additional resist layer (AR) that is optionally applied over the second package layer.
5 . The wafer level package of claim 1 , wherein the first package layer is formed of SiO 2 or SiN.
6 . The wafer level package of claim 1 , wherein the device structures are acoustic resonators (R) and wherein the interconnect structures comprise copper (Cu) pillars or solder bumps.
7 . The wafer level package of claim 1 ,
wherein the second package layer has a planar surface parallel to a substrate surface and comprises a photosensitive resist.
8 . The wafer level package of claim 1 , wherein the interconnect structure and the substrate have a common edge vertical to the surface of the substrate.
9 . The wafer level package of claim 1 , wherein the first package layer, the second package layer, and an optional additional dielectric layer on top of the second package layer have non-coincident structure edges, and wherein a complete surface of the first package layer is covered by one or more of the second package layer or the additional dielectric layer.
10 . The wafer level package of claim 1 , wherein a plurality of gaps are disposed between structure edges of the first package layer and respective circumferences of any interconnect structure surrounded by corresponding structure edges of the first package layer.