IP Library Granted Patent US 12,464,150
Granted Patent B2
US 12,464,150 · App. 17/779,212 · Granted Nov 4, 2025

Methods and apparatus for performing real-time VVC decoding

Inventors: Srinivas Gudumasu (San Diego, CA); Saurav Bandyopadhyay (San Diego, CA); Yuwen He (San Diego, CA); Yong He (San Diego, CA)
Assignee: INTERDIGITAL VC HOLDINGS, INC.
H04N19/436H04N19/124H04N19/139H04N19/159H04N19/176H04N19/52H04N19/593H04N19/82H04N19/96
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Quick Facts
Patent No.
US 12,464,150
App. No.
17/779,212
Granted
Nov 4, 2025
Kind
B2
Abstract

Apparatus and methods for implementing a real-time Versatile Video Coding (VVC) decoder use multiple threads to address the limitation with existing parallelization techniques and fully utilizes the available CPU computation resource without compromising on the coding efficiency. The proposed Multi-threaded (MT) framework uses CTU level parallel processing techniques without compromising on the memory bandwidth. Picture level parallel processing separates the sequence into temporal levels by considering the picture's referencing hierarchy. Embodiments are provided using various optimization techniques to achieve real-time VVC decoding on heterogenous platforms with multi-core CPUs, for those bitstreams generated using a VVC reference encoder with a default configuration.

Claims (20)

1 . A method of parallel decoding of video, comprising:

generating motion vectors for a coding unit;

performing inter coding unit reconstruction;

performing intra coding unit reconstruction; and

performing inverse reshaping and in-loop filter of said video,

wherein said generating and performing steps are performed concurrently on distinct portions of the video, wherein decoder motion vector refinement is used when a length of a motion vector is less than a threshold.

2 . The method of claim 1 , wherein motion vector generation is based on a left, top and/or top right neighboring coding unit.

3 . The method of claim 1 , wherein generation of motion vectors for a top right coding tree unit completes before proceeding to a current coding tree unit motion vector generation.

4 . The method of claim 1 , wherein inter coded coding unit reconstruction is performed separately from intra mode and combined inter and intra prediction mode reconstruction.

5 . The method of claim 1 , wherein a coding unit reconstruction is performed over one or more portions of the coding unit in parallel.

6 . The method of claim 1 , wherein decoder motion vector refinement is used when a length of a motion vector is less than a threshold.

7 . A device, comprising:

memory; and, one or more processors, configured to

generate motion vectors for a coding unit;

perform inter coding unit reconstruction;

perform intra coding unit reconstruction; and

perform inverse reshaping and in-loop filter of said video,

wherein the device is configured to said generate and perform concurrently on distinct portions of the video, wherein decoder motion vector refinement is used when a length of a motion vector is less than a threshold.

8 . A non-transitory computer readable medium containing data content decoded according to the method of claim 1 , for playback using a processor.

9 . A computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the method of claim 1 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 11, 2024
From: VID SCALE, INC.
To: INTERDIGITAL VC HOLDINGS, INC.
Reel/Frame 068284/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2022
From: GUDUMASU, SRINIVAS; BANDYOPADHYAY, SAURAV; HE, YUWEN; HE, YONG; SRIVASTAVA, ASIT
To: VID SCALE, INC.
Reel/Frame 060087/0350 →
Continuity (2)
Provisional Application 62939858 · Nov 25, 2019
Related Publication 20230007283A1 · Jan 5, 2023
References Cited (30)
US 20080165864A1 · Eleftheriadis et al. · 2008 [cited by applicant]
US 20120250772A1 · Gao et al. · 2012 [cited by applicant]
US 20140153635A1 · Zhang et al. · 2014 [cited by applicant]
US 20180124399A1 · Su · 2018 [cited by applicant]
CN 103124345 · 2013 [cited by applicant]
CN 104038766 · 2014 [cited by applicant]
CN 105992008 · 2016 [cited by applicant]
CN 111314777 · 2020 [cited by applicant]
JP 2007219577 · 2007 [cited by applicant]
WO 2016057817 · 2016 [cited by applicant]
Chen et al. (Title: Algorithm description for Versatile Video Coding and Test Model 6 (VTM 6), Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11 15th Meeting: Gothenburg, SE, Jul. 3-12, 2… [cited by examiner]
Chen et al., CE4-Related: Modified History-Based MVP to Support Parallel Processing, Document JVET-10106, Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, 12th Meeting, Macao, CN, Oct. … [cited by applicant]
Zhou et al., AHG4: Enable Parallel Decoding With Tiles, Document: JCTVC-l0118 M24357, Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11 9th Meeting: Geneva, Switzerland, Apr.… [cited by applicant]
ITU-T Recommendation H.264, “Series H: Audiovisual and Multimedia Systems Infrastructure of audiovisual services—Coding of moving video, Advanced video coding for generic audiovisual services”, Telecommunication Standar… [cited by applicant]
Chen et al., “Algorithm description for Versatile Video Coding and Test Model 6 (VTM 6)”, Joint Video Experts Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, Document: JVET-O2002-v2, 15th Meeting: Gothenb… [cited by applicant]
Bross, et al., “High Efficiency Video Coding (HEVC) Text Specification Draft 10 (for FDIS and Last Call)”. Joint Collaborative Team on Video Coding (JCT-VC), Document No. JCTVC-L1003. Jan. 2013, 310 pages. [cited by applicant]
De Souza et al., GPU-Assisted HEVC Intra Decoder, J Real-Time Image Proc, (2016), vol. 12, pp. 531-547. [cited by applicant]
De Souza et al., HEVC In-Loop Filters GPU Parallelization in Embedded Systems, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XV), 2015, pp. 123-130. [cited by applicant]
De Souza et al., Cooperative CPU+GPU Deblocking Filter Parallelization For High Performance HEVC Video Codecs, 2014 IEEE International Conferencee on Acoustic, Speec and Signal Processing (IACASSP), pp. 4993-4997. [cited by applicant]
Alshina et al., “Known Tools Performance Investigation for Next Generation Video Coding”, Document VCEG-AZ05, ITU-Telecommunication Standardization Sector, Study Group 16 Question 6, Video Coding Experts Group (VCEG), 5… [cited by applicant]
Gudumasu et al., [AHG16] VVC Multi-Thread Decoder and Performance Analysis, Joint Video Experts Team (JVET) of ITU-T SG 16 WP3 and ISO/IEC JTC 1/SC 29/WG 11, 18th MeetingP: by Teleconference, Apr. 15-24, 2020, Document:… [cited by applicant]
Zhang et al., Design and Implementation of Parallel Algorithms for Sample Adaptive Offset in HEVC Based on GPU, Sixth International Conference on Information Science and Technology Dalian, China, May 6-8, 2016, pp. 181-… [cited by applicant]
Segall et al., “Joint Call for Proposals on Video Compression with Capability beyond HEVC”, Joint Video Exploration Team (JVET) of ITU-T SG 16 WP 3 and ISO/IEC JTC 1/SC 29/WG 11, Doc. JVET-H1002 (v6), 8th Meeting: Macao… [cited by applicant]
Chen, Jianle, et al., “Coding Tools Investigation for Next Generation Video Coding Based on HEVC”. Applications of Digital Image Processing XXXVIII, vol. 9599, International Society for Optics and Photonics, (2015), pp.… [cited by applicant]
VC-1 Compressed Video Bitstream Format and Decoding Process—Amendment 2, SMPTE Standard, Amendment 2:2011 to SMPTE ST 421M:2006, pp. 1-5. [cited by applicant]
Introduction to Information Communication, First Edition, Corona Publishing Co., Ltd., Oct. 26, 2016, pp. 39 to 44, ISBN: 978-4-339-02857-7, Edited by Takao Waho. [cited by applicant]
H.265/HEVC Textbook, First Edition, Oct. 21, 2013, Impress Japan Co., Ltd., pp. 146 to 148, ISBN: 978-4-8443-3468-2, Edited by Sakae Okubo. [cited by applicant]
Hamidouche et al., Parallel SHVC Decoder: Implementation and Analysis, Proceedings of 2014 IEEE International Conference on Multimedia and Expo (ICME), IEEE, Sep. 8, 2014, 6 pages, ISBN: 978-1-4799-4761-4. [cited by applicant]
Gudumasu, et al. Real-time SHVC Software Decoding with Multi-threaded Parallel Processing , Proceedings of SPIE , SPIE , vol. 9217, pp. 92171R-1 to 92171R-14 , ISSN: 0277-786X, (abstract). [cited by applicant]
Chi, et al., Parallel Scalability and Efficiency of HEVC Parallelization Approaches, IEEE Transactions on Circuits and Systems for Video Technology, IEEE, Dec. 9, 2012, vol. 22, No. 12, pp. 1827-1838. [cited by applicant]