System and method for managing channel bandwidth of a communication signal
Embodiments of systems and methods for managing channel bandwidth of signals are provided herein. Example method include receiving signals from one or more antenna feeds, each signal having a first bandwidth. Some example methods include, in a plurality of processing blocks operating in parallel in one or more processors, performing one or more channelizer operations on portions of the signals, each channelizer operation creates a plurality of channels having a bandwidth smaller than the first bandwidth. Some methods may include, in a plurality of processing blocks in the one or more processors, performing one or more combiner operations on the channels, each operation combines the bandwidth of a subset of the channels into a combined channel, the plurality of processing blocks operating in parallel. The method then outputs the combined channel to a network.
1. A method for managing channel bandwidth of one or more downlink signals, the method comprising:
receiving the one or more downlink signals from one or more antenna feeds, the one or more downlink signals having a first bandwidth;
in a first one or more processing blocks in one or more processors,
performing a first channelizer operation on a first portion of the one or more downlink signals that creates a first plurality of channels, each of the first plurality of channels having a bandwidth smaller than the first bandwidth;
in a second one or more processing blocks in the one or more processors in parallel with the first one or more processing blocks,
performing a second channelizer operation on a second portion of the one or more downlink signals that creates a second plurality of channels, each of the second plurality of channels having a bandwidth smaller than the first bandwidth; and
outputting the first and second plurality of channels to a network.
2. The method of claim 1 , wherein the first one or more processing blocks comprises a first one or more central processing unit (CPU) cores and the second one or more processing blocks comprises a second one or more CPU cores.
3. The method of claim 1 , wherein the one or more processors comprises a plurality of processors, wherein in the first one or more processing blocks are comprised in a first processor of the plurality of processors and the second one or more processing blocks are comprised in a second processor of the plurality of processors.
4. The method of claim 1 , wherein the one or more processors comprises a single processor comprising the first one or more processing blocks and the second one or more processing blocks.
5. The method of claim 1 , wherein the first channelizer operation comprises a first plurality of functions including:
ingesting samples from an input channel, the samples received as first data packets included in the first portion of the one or more downlink signals;
applying a multiple path filter on the samples;
executing a multiple point circular buffer on the filtered samples; and
separating the samples into multiple channels based on applying a multiple point Inverse Fast Fourier Transform to the samples.
6. The method of claim 5 , wherein the first one or more processing blocks comprises a first plurality of processing blocks, wherein performing the first channelizer operation comprises distributing the first plurality of functions amongst the first plurality of processing blocks and performing the distributed first plurality of functions in parallel.
7. The method of claim 5 , wherein the second channelizer operation comprises a second plurality of functions including:
ingesting samples from an input channel, the samples received as second data packets included in the second portion of the one or more downlink signals;
applying a multiple path filter on the samples;
executing a multiple point circular buffer on the filtered samples; and
separating the samples into multiple channels based on applying a multiple point Inverse Fast Fourier Transform to the samples.
8. The method of claim 7 , wherein the second one or more processing blocks comprises a second plurality of processing blocks, wherein performing the second channelizer operation comprises distributing the second plurality of functions amongst the second plurality of processing blocks and performing the distributed second plurality of functions in parallel.
9. The method of claim 8 , wherein one or more of the second plurality of functions are performed in the second one or more processing blocks in parallel with one or more of the first plurality of functions performed in the first one or more processing blocks.
10. The method of claim 1 , further comprising dividing, at one or more processors, the digital bit stream into a plurality of data packets, each of the data packets of the plurality of data packets including an overlap of data from an adjacent packet.
11. The method of claim 1 , wherein the one or more processors are one or more general-purpose central processing units (CPU).
12. The method of claim 1 , wherein the one or more processors employ single instructions, multiple data (SIMD) techniques to achieve high throughput.