Integrated gate-commutated thyristor (IGCT)

1. An integrated gate-commutated thyristor (IGCT) comprising:

a semiconductor wafer having a first main side and a second main side opposite to the first main side;

a plurality of first type thyristor cells and second type thyristor cells, each of the plurality of first type thyristor cells and second type thyristor cells comprising in order from the first main side to the second main side:

a cathode region of a first conductivity type;

a base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the base layer to form a first p-n junction between the base layer and the cathode region;

a drift layer of the first conductivity type forming a second p-n junction with the base layer; and

an anode layer of the second conductivity type separated from the base layer by the drift layer;

wherein the plurality of first type thyristor cells and second type thyristor cells each further comprise:

a gate electrode arranged laterally with respect to the cathode region, the gate electrode forming an ohmic contact with the base layer;

a cathode electrode arranged on the first main side, the cathode electrodes of the plurality of first type thyristor cells forming an ohmic contact with the cathode region and the cathode electrodes of the plurality of second type thyristor cells being insulated from the cathode region; and

an anode electrode arranged on the second main side and forming an ohmic contact with the anode layer;

wherein the cathode electrodes of the plurality of first type thyristor cells and second type thyristor cells are arranged in a segmented circular layout;

wherein the segmented circular layout comprises multiple concentric segment rings increasing in diameter from the center of the segmented circular layout;

wherein the cathode electrodes of the plurality of first type thyristor cells and second type thyristor cells are radially oriented and are circularly arranged within the concentric segment rings;

wherein a predefined percentage of second type thyristor cells of the overall amount of first type thyristor cells and second type thyristor cells in a segment ring is greater than 0% and less than or equal to 75%; and

wherein the segmented circular layout is configured so that, for the concentric segment rings, the predefined percentage decreases with increasing diameter.

2. The IGCT according to claim 1 , wherein the segmented circular layout is configured so that, for the concentric segment rings, the predefined percentage decreases monotonically with increasing diameter.

3. The IGCT according to claim 1 , wherein the predefined percentage within each of the concentric segment rings is equally distributed in a circular direction.

4. The IGCT according to claim 1 , further comprising a gate contact electrically contacting the gate electrodes, the gate contact being located radially outside of the concentric segment rings.

5. The IGCT according to claim 4 , wherein the predefined percentage increases for the concentric segment rings with increasing diameter to a maximum amount and then the predefined percentage decreases for the concentric segment rings with increasing diameter.

6. The IGCT according to claim 1 , further comprising a gate contact electrically contacting the gate electrodes, the gate contact being located in the center of the concentric segment rings.

7. An integrated gate-commutated thyristor (IGCT) comprising:

a semiconductor wafer having a first main side and a second main side opposite to the first main side;

a plurality of first type thyristor cells and second type thyristor cells, each of the plurality of first type thyristor cells and second type thyristor cells comprising in order from the first main side to the second main side:

a cathode region of a first conductivity type;

a base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the base layer to form a first p-n junction between the base layer and the cathode region;

a drift layer of the first conductivity type forming a second p-n junction with the base layer; and

an anode layer of the second conductivity type separated from the base layer by the drift layer;

wherein the plurality of first type thyristor cells and second type thyristor cells each further comprise:

a gate electrode arranged laterally with respect to the cathode region, the gate electrode forming an ohmic contact with the base layer;

a cathode electrode arranged on the first main side, the cathode electrodes of the plurality of first type thyristor cells forming an ohmic contact with the cathode region and the cathode electrodes of the plurality of second type thyristor cells being insulated from the cathode region; and

an anode electrode arranged on the second main side and forming an ohmic contact with the anode layer;

wherein the cathode electrodes of the plurality of first type thyristor cells and second type thyristor cells are arranged in a segmented circular layout;

wherein the segmented circular layout comprises multiple concentric segment rings increasing in diameter from the center of the segmented circular layout;

wherein the cathode electrodes of the plurality of first type thyristor cells and second type thyristor cells are radially oriented and are circularly arranged within the concentric segment rings;

wherein a predefined percentage of second type thyristor cells of the overall amount of first type thyristor cells and second type thyristor cells in a segment ring is greater than 0% and less than or equal to 75%;

wherein the segmented circular layout is configured so that, for the concentric segment rings, the predefined percentage decreases with increasing diameter;

wherein the segmented circular layout comprises at least three concentric segment rings; and

wherein the predefined percentage is not equal for each of the concentric segment rings and forms a maximum somewhere between the innermost and the outermost concentric segment ring.

8. The IGCT according to claim 7 , wherein the segmented circular layout is configured so that, for the concentric segment rings, the predefined percentage decreases monotonically with increasing diameter.

9. The IGCT according to claim 7 , wherein the predefined percentage within each of the concentric segment rings is equally distributed in a circular direction.

10. The IGCT according to claim 7 , further comprising a gate contact electrically contacting the gate electrodes, the gate contact being located radially outside of the concentric segment rings.

11. The IGCT according to claim 10 , wherein the predefined percentage increases for the concentric segment rings with increasing diameter to a maximum amount and then the predefined percentage decreases for the concentric segment rings with increasing diameter.

12. The IGCT according to claim 7 , further comprising a gate contact electrically contacting the gate electrodes, the gate contact being located in the center of the concentric segment rings.

13. A method of manufacturing an integrated gate-commutated thyristor (IGCT),

forming a plurality of semiconductor regions in a semiconductor wafer for first type thyristor cells and second type thyristor cells, the semiconductor regions comprising in order from a first main side of the semiconductor wafer to a second main side of the semiconductor wafer:

a cathode region of a first conductivity type;

a base layer of a second conductivity type different from the first conductivity type, wherein the cathode region is formed as a well in the base layer to form a first p-n junction between the base layer and the cathode region;

a drift layer of the first conductivity type forming a second p-n junction with the base layer; and

an anode layer of the second conductivity type separated from the base layer by the drift layer;

forming a gate electrode for each thyristor, the gate electrodes arranged laterally with respect to the cathode region and forming an ohmic contact with the base layer;

forming a cathode electrode for each thyristor, the cathode electrodes arranged on the first main side of the semiconductor wafer, wherein the cathode electrodes of the first type thyristor cells form an ohmic contact with the cathode region and the cathode electrodes of the second type thyristor cells are insulated from the cathode region; and

forming an anode electrode for each thyristor, the anode electrodes arranged on the second main side and forming an ohmic contact with the anode layer;

wherein the cathode electrodes of the first type thyristor cells and second type thyristor cells are arranged in a segmented circular layout;

wherein the segmented circular layout comprises multiple concentric segment rings increasing in diameter from the center of the segmented circular layout;

wherein the cathode electrodes of the first type thyristor cells and second type thyristor cells are radially oriented and are circularly arranged within the concentric segment rings;

wherein a predefined percentage of second type thyristor cells of the overall amount of first type thyristor cells and second type thyristor cells in a segment ring is greater than 0% and less than or equal to 75%; and

wherein the segmented circular layout is configured so that, for the concentric segment rings, the predefined percentage decreases with increasing diameter.

14. The method of claim 13 , further comprising:

forming a gate dielectric on the first main side of the semiconductor wafer; and

structuring the gate dielectric to form ohmic contacts of the gate electrodes with the base layer and to form ohmic contacts of the cathode electrode of the plurality of the first type thyristor cells with the cathode region, wherein the cathode electrodes of the second type thyristor cells are formed by not removing the gate dielectric for the cathode electrodes of the second type thyristor cells.

15. The method of claim 13 , wherein the segmented circular layout comprises at least three concentric segment rings and wherein the predefined percentage is not equal for each of the concentric segment rings and forms a maximum somewhere between the innermost and the outermost concentric segment ring.

16. The method of claim 13 , wherein the segmented circular layout is configured so that, for the concentric segment rings, the predefined percentage decreases monotonically with increasing diameter.

17. The method of claim 13 , wherein the predefined percentage within each of the concentric segment rings is equally distributed in a circular direction.

18. The method of claim 13 , further comprising forming a gate contact electrically contacting the gate electrodes, the gate contact being located radially outside of the concentric segment rings.

19. The method of claim 18 , wherein the predefined percentage increases for the concentric segment rings with increasing diameter to a maximum amount and then the predefined percentage decreases for the concentric segment rings with increasing diameter.

20. The method of claim 13 , further comprising forming a gate contact electrically contacting the gate electrodes, the gate contact being located in the center of the concentric segment rings.