Adaptive clock signal frequency scaling

1. Adaptive frequency scaling circuitry configured to generate a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency, the adaptive frequency scaling circuitry comprising:

scaling control circuitry comprising hardware configured to:

identify a hardware operating parameter of the data processing system;

adjust the dynamic clock signal frequency of the dynamic clock signal in view of the hardware operating parameter of the data processing system; and

select a dynamic clock gating control value indicative of an integer N; and

clock gating circuitry comprising:

accumulator circuitry having M+1 bits, wherein the accumulator is configured to combine a first input value and a second input value and output M+1 bits corresponding to a sum of the first value and the second value, further wherein the first input value is N;

register circuitry configured to store bits M−1 to 0 of the output M+1 bits from the accumulator and provide the stored bits to the accumulator as the second value; and

gate circuitry configured to output the dynamic clock signal by passing an input clock signal pulse in response to bit M in the output M+1 bits from the accumulator being 1, wherein the scaling control circuitry is configured to determine N based at least on a desired frequency and M.

2. The adaptive frequency scaling circuitry of claim 1 , the hardware operating parameter of the data processing system including at least one of a number of active links, or a buffer usage.

3. The adaptive frequency scaling circuitry of claim 1 , wherein identifying the hardware operating parameter of the data processing system includes receiving a performance indicator that is indicative of the hardware operating parameter of the data processing system.

4. The adaptive frequency scaling circuitry of claim 3 , the performance indicator including at least one of a link rate, a link activity, or a queue length.

5. The adaptive frequency scaling circuitry of claim 3 , the dynamic clock gating control value being used to generate the dynamic clock signal.

6. The adaptive frequency scaling circuitry of claim 5 , the dynamic clock signal being generated by selectively gating the input clock signal based on the dynamic clock gating control value.

7. The adaptive frequency scaling circuitry of claim 5 , the dynamic clock gating control value being periodically updated after a predetermined number of clock cycles.

8. The adaptive frequency scaling circuitry of claim 7 , the dynamic clock signal being updated based on an update of the dynamic clock gating control value.

9. The adaptive frequency scaling circuitry of claim 1 , wherein the dynamic clock signal is generated based on a value obtained from a lookup table.

10. The adaptive frequency scaling circuitry of claim 9 , wherein the value is obtained from a lookup table in view of the hardware operating parameter or a performance indicator.

11. A method, comprising:

receiving a hardware operating parameter of a data processing system;

adjusting a dynamic clock signal frequency of a dynamic clock signal in view of the hardware operating parameter of the data processing system; and

gating the dynamic clock signal by:

inputting M+1 bits corresponding to a dynamic clock gating control value to an accumulator having M+1 bits;

inputting M bits corresponding to bits M−1:0 of the accumulator at a prior input clock cycle to the accumulator; and

passing an input clock signal pulse.

12. The method of claim 11 , wherein receiving the hardware operating parameter of a data processing system includes receiving a performance indicator value indicative of the hardware operating parameter.

13. The method of claim 12 , further comprising selecting the dynamic dock gating control value based at least on the performance indicator value; wherein selecting a dynamic clock gating control value comprises inputting the performance indicator value to a lookup table and selecting an output of the lookup table as the clock gating control value.

14. The method of claim 13 , further comprising:

selecting a fixed clock gating control value based on the dynamic clock gating control value and a fixed clock frequency,

wherein the dynamic clock signal is gated based at least on the fixed clock gating control value to generate a fixed clock signal having the fixed clock frequency.

15. The method of claim 14 , wherein gating the input clock signal to generate the dynamic clock signal for each cycle of the input clock signal.

16. The method of claim 14 , further comprising determining the dynamic clock gating control value as a product of a desired dynamic clock signal frequency and 2 M divided by an input clock frequency of the input clock signal.

17. The method of claim 12 wherein the performance indicator value is indicative of one or more of a highest interface rate amongst active links between the data processing system and external devices, a highest interface rate amongst active links between the data processing system and the external devices, and a queue length in a shared packet buffer in the data processing system.

18. The method of claim 11 , further comprising:

receiving a performance indicator value indicative of a plurality of operating parameters of a data processing system;

determining a plurality of dynamic clock gating control values, wherein each of the determined dynamic clock gating control values in the plurality of dynamic clock gating control values is based a different one of the plurality performance indicator values;

selecting a maximum dynamic clock gating control value from amongst the determined dynamic clock gating control values; and

gating an input clock signal based at least on the maximum dynamic clock gating control value to generate the dynamic clock signal.