EDGE RATE (RISE AND FALL TIME) CONTROLLED SEGMENTED LASER DRIVER
An optical driver circuit is described herein having a plurality of drive cells and delay segments between their control signals resulting in the control of the rising and falling edge rates for an optical device driven by the optical driver circuit.
1 . An optical driver circuit comprising:
a light generating device;
a plurality of drive cells each in a current path of the light generating device;
an enable control signal input logically interfaced to each drive cell, wherein the enable control signal input is adapted to receive an enable control signal; and
at least one delay segment logically between at least one of the drive cells and the enable control signal input.
2 . The optical driver circuit of claim 1 , wherein each drive cell includes an enable transistor in the current path of the light generating device and is logically interfaced to the enable control signal input.
3 . The optical driver circuit of claim 1 , wherein the plurality of drive cells are configured in parallel with respect to each other, such that each drive cell is adapted to pass a fraction of a total current through the light generating device.
4 . The optical driver circuit of claim 1 , wherein the light generating device is a laser.
5 . The optical driver circuit of claim 1 , wherein at least one of the plurality of drive cells further comprises a bias control transistor.
6 . The optical driver circuit of claim 1 , wherein the at least one delay segment is adapted to provide a logic delay of the enable control signal.
7 . The optical driver circuit of claim 1 , wherein an input of a logic low to a logic high transition at the enable control signal input results in a step-wise ascending function for a current through the light generating device.
8 . The optical driver circuit of claim 7 , wherein the time width of a step within the step-wise ascending function is equal to a time delay associated with the at least one delay segment, respectively.
9 . The optical driver circuit of claim 1 , wherein an input of a logic high to a logic low transition at the enable control signal input results in a step-wise descending function for a current through the light generating device.
10 . The optical driver circuit of claim 1 , wherein the at least one delay segment includes at least one of a shift register, a buffer, and/or a timer.
11 . The optical driver circuit of claim 1 , wherein the at least one delay segment has an associated logic time delay.
12 . The optical driver circuit of claim 1 , wherein the time delay is configurable.
13 . A method of modifying edge rates in an optical driver circuit, the optical driver circuit including a light generating device, a plurality of drive cells each in a current path of the light generating device, an enable control signal input logically interfaced to each drive cells, the method comprising:
providing an enable control signal to the enable control signal input;
communicating the enable control signal to a first drive cell of the plurality of drive cells;
delaying the enable control signal to create a delayed enable control signal; and
communicating the delayed control signal to a second drive cell of the plurality of drive cells.
14 . The method of claim 13 , wherein delaying the enable control signal to create a delayed enable control signal is performed by at least one delay segment.
15 . The optical driver circuit of claim 14 , wherein the at least one delay segment includes at least one of a shift register, a buffer, and/or a timer.
16 . The method of claim 13 , further comprising passing a step-wise function for a current through the light generating device.
17 . The optical driver circuit of claim 16 , wherein the enable control signal includes a logic low to a logic high transition and the step-wise function is an ascending step-wise function.
18 . The optical driver circuit of claim 16 , wherein the enable control signal includes a logic high to a logic low transition and the step-wise function is a descending step-wise function.
19 . The method of claim 13 , further comprising delaying the delayed control signal to create a further delayed enable control signal and communicating the further delayed control signal to a third drive cell of the plurality of drive cells.
20 . The method of claim 13 , further comprising delaying the delayed control signal sequentially an integer number “n” times to create a further n delayed enable control signals and communicating the further n delayed control signals to a plurality of drive cells, respectively.