Method and apparatus for synchronizing frequency in remote terminals
View Patent ↗An apparatus for synchronizing frequency to a symbol timing, the apparatus including: a master oscillator to generate a master clock signal; an interpolator to accumulate a frequency error estimate between a symbol timing frequency and the master clock signal; and a frequency controller to transfer a portion of the frequency error estimate to the master oscillator to obtain a lock between the symbol timing and the master clock signal of the master oscillator in a manner that zeros-out the frequency error estimate.
1. An apparatus for synchronizing frequency to a symbol timing, the apparatus comprising:
a master oscillator to generate a master clock signal;
an accumulator to accumulate a frequency error estimate between a symbol timing frequency and the master clock signal; and
a frequency controller to transfer a portion of the frequency error estimate to the master oscillator to obtain a lock between the symbol timing and the master clock signal of the master oscillator in a manner that zeros-out a frequency error,
wherein the accumulator and the master oscillator comprise an outer loop and a negative value of a portion of the frequency error estimate is transferred to an inner loop to adjust the frequency error estimate by the negative value.
2. The apparatus of claim 1 , wherein the master oscillator comprises a Voltage Controlled Crystal Oscillator (VCXO) to control a sampling of the symbol timing by an Analog-to-Digital Converter (A/D).
3. The apparatus of claim 1 , wherein the master oscillator comprises a Numerically Controlled Oscillator (NCO).
4. The apparatus of claim 1 , further comprising a phase lock loop comprising the inner loop comprising a second order loop, wherein an output of the second order loop controls an interpolator.
5. The apparatus of claim 4 , wherein the interpolator periodically samples the symbol timing frequency with a periodicity.
6. The apparatus of claim 4 , wherein the interpolator periodically samples the symbol timing frequency with a periodicity greater than 50 symbols and less than 1000 symbols.
7. The apparatus of claim 1 , wherein the outer loop is driven by the frequency error estimate.
8. The apparatus of claim 1 , wherein the outer loop that is started during a signal acquisition of a received signal.
9. The apparatus of claim 1 , wherein the portion of the frequency error estimate transferred to the master oscillator is subtracted from the frequency error estimate.
10. The apparatus of claim 1 , wherein the accumulator comprises a delay element with an adder in a feedback loop.
11. The apparatus of claim 1 , wherein the accumulator comprises a delay element containing a single integrator.
12. The apparatus of claim 1 , wherein the outer loop further comprises the frequency controller.
13. The apparatus of claim 1 , wherein the outer loop is not a phase lock loop and the outer loop is driven by a frequency error estimate from the inner loop.
14. The apparatus of claim 1 , wherein a portion of the frequency error estimate is periodically used to adjust the frequency error estimate of the outer loop.